Error detection on programmable logic resources

• US 7,310,757 B2
• Filed: 10/10/2002
• Issued: 12/18/2007
• Est. Priority Date: 10/11/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ngo, Ninh D., Lee, Andy L., Veenstra, Kerry
• Primary Examiner(s): Britt; Cynthia
• Assistant Examiner(s): Tabone, Jr.; John J.
• Application Number:
  US10/270,711
• Publication Number:
  US 20030097628A1
• Time in Patent Office: 1,895 Days
• Field of Search: 714/766, 714/799, 714/800, 714/801, 714/807
• US Class Current: 714/725
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Claims

1. A circuit that detects errors only in configuration data stored on a logic device, the logic device comprising:

a first memory in which the configuration data is stored;

a second memory in which an expected value is stored, wherein the expected value is calculated on the logic device from the configuration data at the time the configuration data is being programmed onto the logic device; and

check circuitry coupled to the first memory and the second memory to analyze the configuration data stored in the first memory and the expected value stored in the second memory to determine if any values of the configuration data have changed after initial configuration of the first memory.

2. The logic device of claim 1 wherein the memory is random access memory.

3. The logic device of claim 1 wherein the check circuitry comprises:

checksum circuitry that computes a value based on the configuration data; and

comparison circuitry coupled to the checksum circuitry that compares the computed value to an expected value.

4. The logic device of claim 3 wherein the computed value is a remainder that results from dividing a value based on the configuration data by a predetermined value.

5. The logic device of claim 3 wherein the expected value is a remainder that results from dividing a value based on the configuration data by a predetermined value, wherein the expected value is computed by the checksum circuitry while the configuration data is being programmed onto the logic device.

6. The logic device of claim 3 wherein the comparison circuitry provides one of:

a first signal indicating that no error was detected; and

a second signal indicating that an error was detected.

7. The logic device of claim 1 wherein the check circuitry comprises:

compute circuitry that computes a value based on the configuration data; and

logic circuitry coupled to the compute circuitry that performs a logical operation on the computed value.

8. The logic device of claim 7 wherein the computed value is a remainder that results from dividing a value based on the configuration data and an expected value by a predetermined value.

9. The logic device of claim 8 wherein the expected value is a remainder that results from dividing a value based on the configuration data by a predetermined value, wherein the expected value is computed by the compute circuitry while the configuration data is being programmed onto the logic device.

10. The logic device of claim 7 wherein the logic circuitry comprises logic that generates one of:

a first signal indicating that no error was detected; and

a second signal indicating that an error was detected.

11. The logic device of claim 1 further comprising:

a third memory coupled to the first memory, wherein the third memory stores a portion of the configuration data.

12. The logic device of claim 11 wherein the check circuitry is coupled to the third memory and performs part of the analysis on the portion of the configuration data.

13. The logic device of claim 1 wherein the expected value is a reminder that results from dividing a value based on the configuration data by predetermined value, wherein the expected value is computed by the check circuitry while the configuration date is being programmed onto the logic device.

14. The logic device of claim 1 further comprising output circuitry coupled to the check circuitry to output a signal that indicates whether an error was detected.

15. A digital signal processing system comprising:

processing circuitry;

a third memory coupled to said processing circuitry; and

the logic device as defined in claim 1.

16. A printed circuit board on which is mounted the logic device as defined in claim 1.

17. The printed circuit board as defined in claim 16 further comprising:

a third memory mounted on the printed circuit board and coupled to the logic device.

18. The printed circuit board defined in claim 17 wherein the third memory contains nonvolatile memory that stores the configuration data that is programmed into the logic device.

19. A method for detecting errors in configuration data programmed into a memory in a logic device, comprising:

computing an expected value in the logic device, at the time the configuration data is being programmed onto the logic device, the expected value being computed from a stream of the configuration data that is being programmed onto the logic device;

inputting to check circuitry a stream bits comprising the configuration data and the expected value; and

analyzing the stream of bits to determine if an error has occurred in the configuration data after initial configuration of the memory.

20. The method of claim 19 wherein computing the expected value comprises calculating a remainder that results from dividing a value based on the configuration data by a predetermined value, wherein the calculating is performed while the configuration data is being programmed onto the logic device.

21. The method of claim 19 wherein analyzing the stream of bits comprises:

computing a value based on the stream of bits; and

performing a logical operation on the computed value.

22. The method of claim 19 further comprising outputting a result of the analysis that indicates whether an error was detected.

23. The method of claim 19 wherein outputting the result comprises one of:

sending a first signal indicating that no error was detected; and

sending a second signal indicating that an error was detected.

24. A circuit that detects errors in configuration data stored on a logic device, the logic device comprising:

memory in which the configuration data its stored;

a multiplexer that takes as input the configuration data and an expected value, wherein the expected value is calculated on the logic device from the configuration data at the time the configuration data is being programmed onto the logic device, wherein the multiplexer is operative to output a stream of bits comprising the configuration data and the expected value; and

check circuitry coupled to the multiplexer to analyze the stream of bits to determine if error has occurred in the configuration data after initial configuration of the memory.

25. The logic device of claim 24 wherein the memory is random access memory.

26. The logic device of claim 24 wherein the expected value is calculated from the configuration data used to configure the logic device.

27. The logic device of claim 24 wherein the expected value is a remainder that results from dividing a value based on the configuration data by a predetermined value, wherein the expected value is computed by the check circuitry while the configuration data is being programmed onto the logic device.

28. The logic device of claim 24 wherein the check circuitry comprises:

compute circuitry that computes a value based on the stream of bits; and

logic circuitry coupled to the computer circuitry that performs a logical operation on the computed value.

29. The logic device of claim 28 wherein the computed value is a remainder that results from q value based on the stream of bits by a predetermined value.

30. The logic device of claim 28 wherein the logic circuitry comprises logic that generates one of:

a first signal indicating that no error was detected; and

a second signal indicating that an error was detected.

31. The logic devices of claim 24 further comprising:

a second memory coupled to the memory, wherein the second memory stores a portion of the configuration data.

32. The logic device of claim 31 wherein the multiplexer is coupled to the second memory and operative to send the portion of the configuration data as part of the stream of bits to perform part of the analysis.

33. The logic device of claim 24 further comprising:

a second memory used to store the expected value that is input to the multiplexer.

34. The logic device of claim 24 further comprising output circuitry coupled to the check circuitry to output a signal that indicates whether an error was detected.

35. A digital signal processing system comprising:

processing circuitry;

a second memory coupled to said processing circuitry; and

the logic device as defined in claim 24.

36. A printed circuit board on which is mounted the logic device as defined in claim 24.

37. The printed circuit board as defined in claim 36 further comprising;

a second memory mounted on the printed circuit board and coupled to the logic device.

38. The printed circuit board defined in claim 37 wherein the second memory contains nonvolatile memory that stores the configuration data that is programed into the logic device.