Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof
First Claim
1. A method of fabricating an interconnection structure in a semiconductor device comprising:
- forming a first active region in a substrate;
forming a second active region in the substrate;
forming a first field region in the substrate disposed between the first active region and the second active region;
forming an interlayer dielectric on the substrate;
forming a first opening in the interlayer dielectric exposing the first active region and the second active region;
filling the first opening with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region;
forming a third active region in the substrate;
forming second and third field areas in the substrate and on opposite sides of the third active region;
forming a first conductive line on the second field area;
forming a second conductive line on the third field area;
forming a second opening in the interlayer dielectric exposing first surfaces of the first conductive line and the second conductive line, wherein the interlayer dielectric remains in a gap between the first and the second conductive lines; and
filling the second opening with a conductive material to form a second unitary interconnection structure contacting the first conductive line and the second conductive line and electrically connecting the first conductive line to the second conductive line.
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Abstract
An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.
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Citations
21 Claims
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1. A method of fabricating an interconnection structure in a semiconductor device comprising:
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forming a first active region in a substrate; forming a second active region in the substrate; forming a first field region in the substrate disposed between the first active region and the second active region; forming an interlayer dielectric on the substrate; forming a first opening in the interlayer dielectric exposing the first active region and the second active region; filling the first opening with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region; forming a third active region in the substrate; forming second and third field areas in the substrate and on opposite sides of the third active region; forming a first conductive line on the second field area; forming a second conductive line on the third field area; forming a second opening in the interlayer dielectric exposing first surfaces of the first conductive line and the second conductive line, wherein the interlayer dielectric remains in a gap between the first and the second conductive lines; and filling the second opening with a conductive material to form a second unitary interconnection structure contacting the first conductive line and the second conductive line and electrically connecting the first conductive line to the second conductive line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of fabricating an interconnection structure in a semiconductor substrate comprising:
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forming a field area defining a first active region, a second active region, a third active region, and a fourth active region in a substrate; forming a gate insulator and a first conductive layer on a surface of the substrate; patterning the first conductive layer and the gate insulator to form a first conductive line and a second conductive line on field regions adjoining both sides of the third active region and to form a gate electrode and gate insulator on the fourth active region; forming heavily doped regions at the first active region, the second active region, the third active region, and the fourth active region using the field area and the gate electrode as an ion implantation mask; forming an interlayer dielectric on the surface of the substrate and on the first conductive line, the second conductive line, and the gate electrode; selectively etching the interlayer dielectric to form a first opening exposing the first active region and the second active region, a second opening exposing top surfaces of the first conductive line and the second conductive line, and a third opening exposing the fourth active region and a top surface of the gate electrode, wherein a portion of the interlayer dielectric remains in a gap between the first and the second conductive lines; and filling the first, second and third openings with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region a second unitary interconnection structure connecting the first conductive line to the second conductive line, and a third unitary interconnection structure connecting the gate electrode to the fourth active region. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification