Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof

• US 7,312,144 B2
• Filed: 09/02/2004
• Issued: 12/25/2007
• Est. Priority Date: 07/26/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Won-Seok, Jung, Soon-Moon, Kim, Sung-Bong, Kwon, Hyung-Shin
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/932,416
• Publication Number:
  US 20050029664A1
• Time in Patent Office: 1,209 Days
• Field of Search: 438/618, 438/598, 438/624, 438/626, 438/631, 438/692, 438/740, 438/597
• US Class Current: 438/618
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

Claims

1. A method of fabricating an interconnection structure in a semiconductor device comprising:

forming a first active region in a substrate;

forming a second active region in the substrate;

forming a first field region in the substrate disposed between the first active region and the second active region;

forming an interlayer dielectric on the substrate;

forming a first opening in the interlayer dielectric exposing the first active region and the second active region;

filling the first opening with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region;

forming a third active region in the substrate;

forming second and third field areas in the substrate and on opposite sides of the third active region;

forming a first conductive line on the second field area;

forming a second conductive line on the third field area;

forming a second opening in the interlayer dielectric exposing first surfaces of the first conductive line and the second conductive line, wherein the interlayer dielectric remains in a gap between the first and the second conductive lines; and

filling the second opening with a conductive material to form a second unitary interconnection structure contacting the first conductive line and the second conductive line and electrically connecting the first conductive line to the second conductive line.

2. The method of claim 1, wherein forming a first opening and forming a second opening comprises:

selectively etching portions of the interlayer dielectric corresponding to the first opening and the second opening until the first surfaces of the first and second conductive lines are exposed so as to form the first opening having a portion of the interlayer dielectric remaining at a bottom of the first opening and so as to form a second opening having a portion of the interlayer dielectric remaining in a gap between the first conductive line and the second conductive line; and

then

selectively etching the portion of the interlayer dielectric corresponding to the first opening so as to remove the portion of the interlayer dielectric remaining at the bottom of the first opening so as to expose the first active region and the second active region at the bottom of the first opening.

3. The method of claim 1, wherein forming an interlayer dielectric comprises:

forming a first interlayer dielectric on the substrate; and

forming a second interlayer dielectric on the first interlayer dielectric.

4. The method of claim 3, wherein forming a first opening and forming a second opening comprises:

selectively etching the second interlayer dielectric until a surface of the first interlayer dielectric is exposed to form the first opening and the second opening;

then

selectively etching a portion of the first interlayer dielectric exposed at a bottom of the first opening to reduce a difference between a thickness of the first interlayer dielectric from the substrate to a bottom of the first opening and a thickness of the first interlayer dielectric from the first surfaces of the first and second conductive lines to a bottom of the second opening; and

then

selectively etching the first interlayer dielectric remaining at bottoms of the first opening and the second opening using the second interlayer dielectric as an etching mask to expose the first active region and the second active region at a bottom of the first opening and to expose the first conductive line and the second conductive line at a bottom of the second opening, wherein a portion of the first interlayer dielectric remains between the first conductive line and the second conductive line.

5. The method of claim 3, wherein forming an interlayer dielectric further comprises forming an etch stop layer disposed between the first interlayer dielectric and the substrate, and wherein forming a first opening and forming a second opening further comprises removing the etch stop layer exposed at a bottom of the first opening and a bottom of the second opening.

6. The method of claim 1, wherein the steps of filling the first opening and filling the second opening are carried out simultaneously.

7. The method of claim 1, wherein the first unitary interconnection structure and the second unitary interconnection structure are made of at least one material selected from the group consisting of tungsten, aluminum, copper, titanium, titanium nitride, and tantalum nitride.

8. The method of claim 1, wherein the first and the second conductive lines are gate electrodes of pass transistors in an SRAM, and the second unitary interconnection is a word line.

9. The method of claim 8, wherein the steps of filling the first opening and filling the second opening are carried out simultaneously.

10. The method of claim 9, wherein the interlayer dielectric comprises a first interlayer dielectric and a second interlayer dielectric that have different etch rates with respect to each other.

11. The method of claim 9, wherein the first and the second conductive lines are pass transistors of an SRAM and the second unitary interconnection structure is a word line connecting the pass transistors.

12. The method of claim 9, wherein at least one of the first active region and/or the second active region is doped with N-type impurities.

13. The method of claim 9, wherein at lease one of the first active region and/or the second active region is doped with P-type impurities.

14. The method of claim 9, wherein the third active region and the second interconnection structure cross each other with the interlayer dielectric disposed therebetween and provide a conductive line, respectively, wherein the interlayer dielectric is interposed in a gap between the first and the second unitary interconnection structures.

15. The method of claim 9, wherein top surfaces of the first and the second conductive lines and a top surface of an interlayer dielectric interposed therebetween are substantially coplanar.

16. A method of fabricating an interconnection structure in a semiconductor substrate comprising:

forming a field area defining a first active region, a second active region, a third active region, and a fourth active region in a substrate;

forming a gate insulator and a first conductive layer on a surface of the substrate;

patterning the first conductive layer and the gate insulator to form a first conductive line and a second conductive line on field regions adjoining both sides of the third active region and to form a gate electrode and gate insulator on the fourth active region;

forming heavily doped regions at the first active region, the second active region, the third active region, and the fourth active region using the field area and the gate electrode as an ion implantation mask;

forming an interlayer dielectric on the surface of the substrate and on the first conductive line, the second conductive line, and the gate electrode;

selectively etching the interlayer dielectric to form a first opening exposing the first active region and the second active region, a second opening exposing top surfaces of the first conductive line and the second conductive line, and a third opening exposing the fourth active region and a top surface of the gate electrode, wherein a portion of the interlayer dielectric remains in a gap between the first and the second conductive lines; and

filling the first, second and third openings with a conductive material to form a first unitary interconnection structure connecting the first active region to the second active region a second unitary interconnection structure connecting the first conductive line to the second conductive line, and a third unitary interconnection structure connecting the gate electrode to the fourth active region.

17. The method of claim 16, wherein forming the first opening, the second opening, and the third opening comprises:

selectively etching the interlayer dielectric until top surfaces of the first conductive line, the second conductive line, and the gate electrode are exposed to form a first opening having a portion of the interlayer dielectric remaining at a bottom thereof, a second opening having a portion of the interlayer dielectric remaining in a gap between the first conductive line and the second conductive line, and a third opening exposing a portion of a top surface of the gate electrode and having a portion of the interlayer dielectric remaining at a bottom of the third opening disposed between the bottom of the third opening and the fourth active region; and

selectively etching the portions of the interlayer dielectric remaining at the bottom of the first and the third openings to expose the first active region and the second active region at a bottom of the first opening and to expose the fourth active region at a bottom of the third opening.

18. The method of claim 16, wherein forming the first, the second, and the third openings comprising:

selectively etching the second interlayer dielectric until a surface of the first interlayer dielectric is exposed to form the first opening, the second opening, and the third opening;

selectively etching a portion of the exposed first interlayer dielectric at a bottom of the first and third openings thereby reducing a difference between a thickness of portions of the first interlayer dielectric at the bottoms of the first and third openings with respect to the substrate and a thickness of a portion of the first interlayer dielectric at the bottom of the second opening with respect to a top surface of the first and second conductive lines; and

then

selectively etching the first interlayer dielectric remaining at a bottom of the first, the second, and the third opening using the second interlayer dielectric as an etching mask to expose the first active region and the second active region at a bottom of the first opening, thereby exposing the first conductive line and the second conductive line at a bottom of the second opening, and exposing the fourth active region at a bottom of the third opening.

19. The method of claim 18, wherein the first unitary interconnection structure, the second unitary interconnection structure, and the third unitary interconnection structure a material selected from the group consisting of tungsten, aluminum, copper, titanium, titanium nitride, and tantalum nitride.

20. The method of claim 16, wherein the first unitary interconnection structure, the second unitary interconnection structure and the unitary third interconnection structure are simultaneously formed and are formed of the same material.

21. The method of claim 16, wherein top surfaces of the interlayer dielectric, the first unitary interconnection structure, the second unitary interconnection structure and the third unitary interconnection structure are substantially coplanar.