Three dimensional integrated circuit
First Claim
Patent Images
1. An integrated circuit (IC) chip comprising:
- a substrate layer;
a first insulating layer on said substrate layer;
a first semiconductor layer on said first insulating layer, transistors being formed from said first semiconductor layer and connected together into circuit elements in a circuit layer;
a second insulating layer attached to said first semiconductor layer;
a second semiconductor layer on said second insulating layer, transistors being formed from said second semiconductor layer, and connected together into an array of circuit elements in a circuit layer, wherein a majority of IC chip elements are located on said first semiconductor layer; and
a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on and extending from one of said circuit elements on said first semiconductor layer and said second semiconductor layer, ones of said circuit elements on said first semiconductor layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second semiconductor layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC;
wherein said circuit elements on said SOI CMOS circuit layer include combinational logic and said array of circuit elements is a CMOS driver grid, selected drivers of said CMOS driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer.
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Abstract
A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
297 Citations
11 Claims
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1. An integrated circuit (IC) chip comprising:
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a substrate layer; a first insulating layer on said substrate layer; a first semiconductor layer on said first insulating layer, transistors being formed from said first semiconductor layer and connected together into circuit elements in a circuit layer; a second insulating layer attached to said first semiconductor layer; a second semiconductor layer on said second insulating layer, transistors being formed from said second semiconductor layer, and connected together into an array of circuit elements in a circuit layer, wherein a majority of IC chip elements are located on said first semiconductor layer; and a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on and extending from one of said circuit elements on said first semiconductor layer and said second semiconductor layer, ones of said circuit elements on said first semiconductor layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second semiconductor layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC; wherein said circuit elements on said SOI CMOS circuit layer include combinational logic and said array of circuit elements is a CMOS driver grid, selected drivers of said CMOS driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A CMOS integrated circuit (IC) chip comprising:
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an SOI circuit layer comprising; a semiconductor substrate layer; an insulating layer on said substrate layer, and a silicon layer on said insulating layer, Field Effect Transistors (FETs) being formed in said silicon layer and connected together into circuit elements in a circuit layer; a second insulating layer attached to said SOI circuit layer; a CMOS driver grid in a second silicon layer on said second insulating layer, wherein a majority of IC chip elements are located on said SOI circuit layer; and a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on and extending from one of said circuit elements in said SOI circuit layer and said second silicon layer, ones of said circuit elements on said SOI circuit layer being connected through said plurality of interlayer connection channels to corresponding ones of said array of circuit elements, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said CMOS IC; and wherein said circuit elements on said SOI circuit layer include combinational logic, selected drivers of said CMOS driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer. - View Dependent Claims (9, 10)
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11. An integrated circuit (IC) comprising:
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a plurality of circuit layers adhesively bonded to one another in a stack and including at least a first circuit layer and a second circuit layer of transistors connected together into circuit elements, wherein said first circuit layer is a silicon on insulator (SOI) CMOS circuit layer, said circuit elements on said SOI CMOS circuit layer comprise combinational logic said second circuit layer includes an array of active circuit elements and said array of active circuit elements is a CMOS driver grid, selected drivers of said driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer; a plurality of said circuit elements on said second circuit layer being disposed directly above a plurality of said circuit elements on first layer; and a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on one of said circuit elements on said first layer and said second layer, ones of said circuit elements on said first layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC.
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Specification