Method for fabricating a DRAM memory cell arrangement having fin field effect transistors and DRAM memory cell

• US 7,312,492 B2
• Filed: 06/29/2005
• Issued: 12/25/2007
• Est. Priority Date: 06/29/2004
• Status: Active Grant

• Current Assignee: ChangXin Memory Technologies, Inc.
• Original Assignee: Infineon Technologies AG
• Inventors: Gruning-Von Schwerin, Ulrike
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Ho, Anthony
• Application Number:
  US11/169,812
• Publication Number:
  US 20060006446A1
• Time in Patent Office: 909 Days
• Field of Search: 257/347, 257/301, 257/302
• US Class Current: 257/301
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench

Abstract

The invention relates to the fabrication of DRAM memory cell arrangements having fin field effect transistors and curved channel field effect transistors. The FinFETs and CFETs are formed in a manner oriented to semiconductor fins arranged in cell rows. Within the cell rows, the semiconductor fins are spaced apart from one another by cell insulator structures. Adjacent cell rows are spaced apart from one another by striplike trench insulator structures. The semiconductor fins are in each case recessed in one or in two inner trench sections by means of gate trenches which extend from a longitudinal side of the respective semiconductor fin to the opposite longitudinal side. By isotropically etching the oxide of the trench insulator structures, pockets (fin trenches) are formed, in a self-aligned manner with respect to the gate trenches in the trench insulator structures and filled with a gate conductor material. Vertical gate electrode sections emerge without etching back from the deposited gate conductor material. In conjunction with trench capacitors as cell insulator structures, an improved decoupling and insulation of the trench capacitors from word lines led above the trench capacitors are achieved.

Claims

1. A transistor comprising:

an active zone formed in a semiconductor fin;

a gate trench structure that is introduced from a fin surface into an inner trench section of the semiconductor fin;

two source/drain regions that are formed in each case as a doped zone in outer sections of the semiconductor fin that adjoin both sides of the gate trench structure, respectively; and

a gate electrode comprising two plate sections wherein the plate sections overlap the active zone uniformly up to an extent of at most half the width of the semiconductor fin and are connected to one another by the gate trench structure formed as trench section of the gate electrode.

2. An array of transistors as claimed in claim 1 that are arranged in each case in cell rows comprising:

in each case precisely one field effect transistor is formed in the semiconductor fins;

the cell rows are spaced apart from one another by a trench insulator structure in each case; and

mutually adjacent cell rows are formed in a manner offset by in each case half a cell length with respect to one another,

the gate electrodes of cell rows that are not formed in an offset manner with respect to one another are formed as sections of word lines running perpendicular to the cell rows.

3. An array of transistors for DRAM memory cell arrangements comprising:

having a plurality of field effect transistors as claimed in claim 1 that are arranged in each case in cell rows, wherein in each case two field effect transistors are formed in a mirror-inverted fashion with respect to one another in the semiconductor fins and in this case a first source/drain region of one field effect transistor and a second source/drain region of the other field effect transistor are provided as a single doped zone;

the cell rows are spaced apart from one another by a trench insulator structure in each case; and

the gate electrodes are formed as sections of word lines running perpendicular to the cell rows.

4. The array of transistors as claimed in claim 3, wherein mutually adjacent cell rows are formed in a manner offset by in each case half a cell length with respect to one another and the word lines are formed in section in each case by the gate electrodes of cell rows that are not formed in an offset manner with respect to one another.

5. The transistor of claim 1, wherein the plate sections are disposed in a self-aligned manner with respect to the gate trench structure.

6. The transistor of claim 1, wherein the plate sections are made of polysilicon.

7. A DRAM memory cell comprising a transistor including:

an active zone formed in a semiconductor fin;

a gate trench structure that is introduced from a fin surface into an inner trench section of the semiconductor fin;

two source/drain regions that are formed in each case as a doped zone in outer sections of the semiconductor fin that adjoin both sides of the gate trench structure, respectively; and

a gate electrode comprising two plate sections, wherein the plate sections extend to below a lower edge of the gate trench structure up to a depth of at most half the width of the semiconductor fin and are connected to one another by the gate trench structure formed as trench section of the gate electrode.

8. The memory cell of claim 7, having a plurality of field effect transistors that are arranged in cell rows comprising:

in each case precisely one field effect transistor is formed in the semiconductor fins;

the cell rows are spaced apart from one another by a trench insulator structure in each case; and

mutually adjacent cell rows are formed in a manner offset by in each case half a cell length with respect to one another,

the gate electrodes of cell rows that are not formed in an offset manner with respect to one another are formed as sections of word lines running perpendicular to the cell rows.

9. A DRAM memory cell arrangement comprising, a transistor comprising:

an active zone formed in a semiconductor fin;

a gate trench structure that is introduced from a fin surface into an inner trench section of the semiconductor fin;

two source/drain regions that are formed as doped zones in outer sections of the semiconductor fin that adjoin both sides of the gate trench structure, respectively; and

a gate electrode comprising two plate sections, wherein the plate sections extend to below a lower edge of the gate trench structure up to a depth of at most half the width of the semiconductor fin and are connected to one another by the gate trench structure formed as trench section of the gate electrode.

10. A transistor comprising:

an active zone formed in a semiconductor fin;

a gate electrode; and

two source/drain regions that are formed as a doped zone in outer sections of the semiconductor fin that adjoin both sides of the gate electrode, respectively,

wherein the gate electrode comprises two plate sections that extend to below a lower edge of an upper side of the semiconductor fin up to a depth of at most half the width of the semiconductor fin.

11. The transistor of claim 10, wherein the plate sections are made of polysilicon.