Chip scale package with heat spreader

• US 7,312,516 B2
• Filed: 01/13/2003
• Issued: 12/25/2007
• Est. Priority Date: 02/23/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Corisis, David J.
• Primary Examiner(s): Pham, Hoai
• Assistant Examiner(s): Nguyen, DiLinh
• Application Number:
  US10/342,632
• Publication Number:
  US 20030080402A1
• Time in Patent Office: 1,807 Days
• Field of Search: 257/666, 257672-676, 257737-738, 257/778, 257/706, 257/707, 257/720, 257/730, 257/667, 257668-670, 257/712, 257/796, 257/677
• US Class Current: 257/676
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/812 Applying energy for connecting
• CPC Class Codes: H01L 2224/81201 Compression bonding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49568 specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Semiconductor dice are bonded to the paddles by, e.g., conventional semiconductor die attachment methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.

Claims

1. An assembly having a semiconductor die adhesively attached to a portion of a paddle frame comprising:

a chip-on-board semiconductor die having an active surface having a plurality of bond pads thereon and an opposing second surface;

at least one projection connected to at least one bond pad of said plurality of bond pads on said active surface of said chip-on-board semiconductor die for direct connection using at least one of a thermal process, a pressure process, and a combination of a thermal process and a pressure process to a substrate, said at least one projection including one of at least one of a piece of wire forming a solder ball and at least one solder bump; and

a generally centrally positioned paddle having a size essentially the same as said chip-on-board semiconductor die, said generally centrally positioned paddle of a paddle frame of a plurality of paddle frames solely having side rails and a plurality of cross-members connected to said generally centrally positioned paddle, said generally centrally positioned paddle for use as a heat sink for said chip-on-board semiconductor die for dissipating heat therefrom when said chip-on-board semiconductor die is mounted on a substrate, said opposing second surface of said chip-on-board semiconductor die being secured to said generally centrally positioned paddle, said generally centrally positioned paddle being attached to said side rails by at least a plurality of paddle support bars and being attached to said cross-members by said at least a plurality of paddle support bars.

2. The assembly of claim 1, wherein said at least one projection includes a plurality of projections comprising a ball grid array (BGA) of solder balls.

3. The assembly of claim 1, wherein said at least one projection comprises at least one ball deposited by a wire bonding machine.

4. The assembly of claim 1, wherein said at least one projection comprises at least one stud bump deposited by a wire bonding machine.

5. The assembly of claim 1, further comprising:

an electrically non-conductive adhesive layer securing said opposing second surface to said generally centrally positioned paddle.

6. The assembly of claim 5, wherein said electrically non-conductive adhesive layer comprises one of epoxy and polyimide.

7. The assembly of claim 1, further comprising:

an electrically conductive adhesive layer securing said opposing second surface of said chip-on-board semiconductor die to said generally centrally positioned paddle.

8. The assembly of claim 7, wherein said electrically conductive adhesive layer comprises a eutectic material.

9. The assembly of claim 7, wherein said electrically conductive adhesive layer comprises a gold-silicon eutectic material.

10. The assembly of claim 7, wherein said electrically conductive adhesive layer comprises a metal-filled polymer, said metal-filled polymer comprising a heat conductive material.

11. The assembly of claim 7, wherein said electrically conductive adhesive layer comprises conductive polyimide.

12. The assembly of claim 1, wherein said substrate includes circuit connections, said plurality of bond pads bonded to said circuit connections.

13. The assembly of claim 12, further comprising:

sealant packaging material enclosing a portion of said chip-on-board semiconductor die and covering a portion of said substrate.

14. An assembly having a semiconductor die adhesively attached to a portion of a paddle frame comprising:

a semiconductor die having an active surface having at least one bond pad thereon and an opposing second surface;

at least one projection secured to said at least one bond pad on said active surface of said semiconductor die for direct connection using at least one of a thermal process, a pressure process, and a combination of a thermal process and a pressure process to a substrate, said at least one projection including one of at least one of a piece of wire forming a solder ball and at least one solder bump; and

a metal paddle having a size essentially the same as said semiconductor die, said metal paddle from a paddle frame having no narrow leads, said opposing second surface of said semiconductor die being attached to said metal paddle, said metal paddle attached to at least one side rail of a paddle frame by at least a plurality of paddle support bars and attached to a plurality of cross-members by said at least a plurality of paddle of support bars.

15. The assembly of claim 14, wherein said at least one projection comprises a ball grid array (BGA) of solder balls.

16. The assembly of claim 14, wherein said at least one projection comprises at least one ball deposited by a wire bonding machine.

17. The assembly of claim 14, wherein said at least one projection comprises at least one stud bump deposited by a wire bonding machine.

18. The assembly of claim 14, further comprising:

an electrically non-conductive adhesive layer attaching said opposing second surface to said metal paddle.

19. The assembly of claim 18, wherein said electrically non-conductive adhesive layer comprises one of epoxy and polyimide.

20. The assembly of claim 14, further comprising:

an electrically conductive adhesive layer attaching said opposing second surface to said metal paddle.

21. The assembly of claim 20, wherein said electrically conductive adhesive layer comprises a eutectic material.

22. The assembly of claim 21, wherein said electrically conductive adhesive layer comprises a metal-filled polymer, said metal-filled polymer comprising a heat conductor.

23. The assembly of claim 21, wherein said electrically conductive layer comprises conductive polyimide.

24. The assembly of claim 20, wherein said electrically conductive adhesive layer comprises a gold-silicon eutectic material.

25. The assembly of claim 14, further comprising:

a substrate having a plurality of circuit connections, said at least one bond pad connected to at least one circuit connection of said plurality of circuit connections.

26. The assembly of claim 25, further comprising:

sealant packaging covering a portion of said semiconductor die and a portion of said substrate.

27. An assembly having a semiconductor die and a portion of a paddle frame comprising:

a chip-on-board semiconductor die having an active surface having a plurality of bond pads thereon and an opposing second surface;

a plurality of projections connected to said plurality of bond pads directly for connection using at least one of a thermal process, a pressure process, and a combination of a thermal process and a pressure process to a host circuit board, said plurality of projections including one of a plurality of pieces of wire forming solder balls and a plurality of solder bumps; and

a metallic paddle having a size essentially the same as said chip-on-board semiconductor die, said metallic paddle secured to said opposing second surface of said chip-on-board semiconductor die for dissipating heat therefrom during operation thereof when said chip-on-board semiconductor die is attached to a substrate, said metallic paddle being attached to at least one side rail of a paddle frame having no narrow leads by at least a plurality of paddle support bars and being attached to a plurality of cross-members by said at least a plurality of support bars.

28. The assembly of claim 27, wherein said plurality of projections comprises a ball grid array (BGA) of solder balls.

29. The assembly of claim 27, wherein said plurality of projections comprises balls deposited by a wire bonding machine.

30. The assembly of claim 27, wherein said plurality of projections comprises a plurality of stud bumps deposited by a wire bonding machine.

31. The assembly of claim 27, further comprising:

an electrically non-conductive adhesive layer connecting said opposing second surface to said metallic paddle.

32. The assembly of claim 31, wherein said electrically non-conductive adhesive layer comprises one of epoxy and polyimide.

33. The assembly of claim 27, further comprising:

an electrically conductive adhesive layer connecting said opposing second surface to said metallic paddle.

34. The assembly of claim 33, wherein said electrically conductive adhesive layer comprises a eutectic material.

35. The assembly of claim 33, wherein said electrically conductive adhesive layer comprises a gold-silicon eutectic material.

36. The assembly of claim 33, wherein said electrically conductive adhesive layer comprises a metal-filled polymer, said metal-filled polymer comprising a heat conductive material.

37. The assembly of claim 33, wherein said electrically conductive adhesive layer comprises conductive polyimide.

38. The assembly of claim 27, further comprising:

a substrate having a plurality of circuit connections, said plurality of bond pads connected to said plurality of circuit connections.

39. The assembly of claim 38, further comprising:

sealant packaging covering a portion of said chip-on-board semiconductor die and a portion of said substrate.