Semiconductor device with holding member

• US 7,312,521 B2
• Filed: 04/23/2003
• Issued: 12/25/2007
• Est. Priority Date: 04/23/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Otagaki, Takayasu, Ando, Tatsuya, Okigawa, Mitsuru, Noma, Takashi, Shinogi, Hiroyuki, Takai, Nobuyuki, Kitagawa, Katsuhiko, Tokushige, Ryoji
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/420,943
• Publication Number:
  US 20030230805A1
• Time in Patent Office: 1,707 Days
• Field of Search: 257/784, 257/783, 257/782, 257/738, 257/737, 257/684, 257/734, 257/758, 257/621, 257/692, 257/693, 257/666, 438/64, 438/109
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Claims

1. A semiconductor device comprising;

a semiconductor die;

a first insulation film disposed on a top surface of the semiconductor die;

a first wiring portion disposed on the first insulation film;

an inorganic holding substrate disposed over the top surface of the semiconductor die;

a separate resin layer attaching the holding substrate to the top surface of the semiconductor die;

a second insulation film comprising a side film and a back film, the side film being disposed on a side surface of the semiconductor die and the back film being disposed on a back surface of the semiconductor die;

a second wiring portion disposed on the side film and the back film and connected to the first wiring portion; and

a conductive terminal formed on the second wiring portion.

2. The semiconductor device of claim 1, wherein the second wiring portion is connected to a side surface of the first wiring portion, the side surface of the first wiring portion being aligned along the thickness direction of the first wiring portion.

3. The semiconductor device of claim 1, wherein the second wiring portion is connected to a back surface of the first wiring portion, the back surface of the first wiring portion facing the first insulation film.

4. The semiconductor device of claim 3, wherein a length of a contacting portion between the second wiring portion and the back surface of the first wiring portion is longer than a thickness of the first wiring portion.

5. The semiconductor device of claim 1, wherein the second wiring portion is connected to a back surface of the first wiring portion and a side surface of the first wiring portion, the side surface of the first wiring portion being aligned along the thickness direction of the first wiring portion and the back surface of the first wiring portion facing the first insulation film.

6. The semiconductor device of claim 5, wherein a length of a contacting portion between the second wiring portion and the back surface of the first wiring portion is longer than a thickness of the first wiring portion.

7. The semiconductor device of claim 1, further comprising a cushion disposed between the second wiring portion and the second insulation film.

8. The semiconductor device of claim 1, wherein the holding substrate is a glass plate, a silicon substrate or a reclaimed silicon substrate.

9. A semiconductor device comprising:

a semiconductor die;

a first insulation film disposed on a top surface of the semiconductor die;

a first wiring portion disposed on the first insulation film;

an inorganic holding substrate disposed over the top surface of the semiconductor die;

a separate resin layer attaching the holding substrate to the top surface of the semiconductor die;

a second insulation film disposed on a side surface and a back surface of the semiconductor die;

a second wiring portion disposed on the second insulation film and being in contact with part of a back surface of the first wiring portion, another part of the back surface of the first wiring portion being in contact with the first insulation film on the top surface of the semiconductor die; and

a conductive terminal formed on the second wiring portion.

10. A semiconductor device comprising:

a semiconductor die;

a first insulation film disposed on a top surface of the semiconductor die;

a first wiring portion disposed on the first insulation film;

a holding substrate having a thickness of about 400 μ

m and attached to the top surface of the semiconductor die;

a second insulation film comprising a side film and a back film, the side film being disposed on a side surface of the semiconductor die and the back film being disposed on a back surface of the semiconductor die;

a second wiring portion disposed on the side film and the back film and connected to the first wiring portion; and

a conductive terminal formed on the second wiring portion.