Wafer level testing for RFID tags

• US 7,312,622 B2
• Filed: 12/15/2004
• Issued: 12/25/2007
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A., Hyde, John D., Kuhn, Jay A., Glidden, Robert M., Horch, Andrew Edward
• Primary Examiner(s): Nguyen; Ha Tran
• Assistant Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US11/014,523
• Publication Number:
  US 20060125507A1
• Time in Patent Office: 1,105 Days
• Field of Search: None
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer'"'"'s scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag'"'"'s non-volatile memory.

Claims

1. A semiconductor wafer, comprising:

a reticle containing circuitry for a plurality of individual semiconductor chips separated by scribe regions, said reticle having at least one die location containing a wafer test probe landing cite to receive test signals to test at least a group of said individual semiconductor chips, said wafer test probe landing cite wired to said individual semiconductor chips through at least one of said scribe regions so that said test signals are transported through said at least one of said scribe regions, wherein, at least one test signal path that flows within one of said at least one scribe regions also includes;

a first wiring element above said wafer'"'"'s semiconductor substrate;

a via coupled to said first element and that makes electrical contact to a conducting path that flows through said substrate beneath a scribe line;

a second via that makes electrical contact to said conducting path on an opposite side of said scribe line from said via; and

a second wiring element above said wafer'"'"'s semiconductor substrate coupled to said second via.

2. The semiconductor wafer of claim 1 wherein said reticle contains more than one die location having a wafer test probe landing cite to receive respective test signals for at least a respective portion of said individual semiconductor chips.

3. The semiconductor wafer of claim 2 where each of said wafer test probe landing cites is coupled to all of said reticle'"'"'s semiconductor chips through wiring that runs through at least a portion of said reticle'"'"'s scribe regions.

4. The semiconductor wafer of claim 1 wherein said at least one die location'"'"'s wafer test probe landing site is said wired to said individual semiconductor chips with a multi-drop bus.

5. The semiconductor wafer of claim 1 wherein said at least one die location'"'"'s wafer test probe landing site is said wired to all semiconductor chips within said reticle.

6. The semiconductor wafer of claim 1 wherein said reticle contains a plurality of die locations each having a wafer test probe landing cite to receive respective, each one of said plurality of die locations residing in a corner of said reticle and its respective wafer test probe landing site wired to the same semiconductor chips.

7. The semiconductor wafer of claim 1 wherein each one of said semiconductor chips is an RFID tag semiconductor chip.

8. The semiconductor wafer of claim 7 wherein said at least one die location includes four die locations each reserved for a wafer test probe landing cite to receive respective test signals for at least a respective portion of said individual RFID tag semiconductor chips, each one of said four die locations residing in a corner of said reticle.

9. The semiconductor wafer of claim 8 where each one of said four die location'"'"'s respective wafer test probe landing site is coupled to all of said reticle'"'"'s RFID tag semiconductor chips through wiring that runs through at least a portion of said reticle'"'"'s scribe and break regions.

10. The semiconductor wafer of claim 7 wherein each one of said at least one die location'"'"'s respective wafer test probe landing site is said wired to said individual RFID tag semiconductor chips with a multi-drop bus.

11. The semiconductor wafer of claim 7 wherein each one of said at least one die location'"'"'s respective wafer test probe landing site is said wired to all RFID tag semiconductor chips within said reticle.

12. The semiconductor wafer of claim 7 wherein each one of said individual RFID tag semiconductor chips comprise a receive signal path from one or more inputs to a controller, said receive signal path to process an electrical receive signal originating from said input(s) as a consequence of said input(s) having received a wireless signal, a second signal path flowing into said receive signal path from a die edge, said second signal path to transport an electrical test signal provided by said wafer test probe.

13. The semiconductor wafer of claim 12 wherein said receive signal path flows through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said second signal path.

14. The semiconductor wafer of claim 12 wherein each of said individual RFID tag semiconductor chips further comprise:

a rectifier coupled to said input(s), a node where a supply voltage for the RFID tag semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to supply voltage wiring that provides a supply voltage provided by said wafer test probe.

15. The semiconductor wafer of claim 14 wherein each of said RFID tag semiconductor chips further comprise:

a multiplexer to multiplex between test signals generated while said RFID tag semiconductor chip is being tested on wafer, said multiplexer having its power supply node coupled to said power supply wiring.

16. The semiconductor wafer of claim 7 wherein said reticle contains one or more die locations each reserved for a wafer test probe to apply and receive respective test signals to a respective portion of said individual RFID tag semiconductor chips, each one of said die locations residing in a corner of said reticle, each of said four redundant die locations wired to the same RFID tag semiconductor chips through one or more redundant busses.

17. The semiconductor wafer of claim 1 wherein said wafer test probe landing cite neighbors one, two, three or four semiconductor chips separated by scribe lines.

18. A semiconductor wafer, comprising:

a reticle containing circuitry for a plurality of individual semiconductor chips separated by scribe regions, said reticle having at least one die location containing a wafer test probe landing cite to receive test signals to test at least a group of said individual semiconductor chips, said wafer test probe landing cite wired to said individual semiconductor chips through at least one of said scribe regions so that said test signals are transported through said at least one of said scribe regions, wherein, each of said individual semiconductor chips comprise a receive signal path from one or more primary inputs to a controller, said receive signal path to process an electrical receive signal originating from said input(s) as a consequence of said input(s) having received a wireless signal, a second signal path flowing into said receive signal path from a die edge, said second signal path to transport an electrical test signal provided from said wafer test probe landing cite.

19. The apparatus of claim 18 wherein said receive signal path flows through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said second signal path.

20. The apparatus of claim 19 wherein each of said individual semiconductor chips further comprise:

a rectifier coupled to said input, a node where a supply voltage for the semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to supply voltage wiring that provides a supply voltage provided by said wafer test probe.

21. The apparatus of claim 20 wherein each of said semiconductor chips further comprise:

a multiplexer to multiplex between test signals generated while said semiconductor chip is being tested on wafer, said multiplexer having its power supply node coupled to said power supply wiring.

22. A semiconductor wafer, comprising:

a reticle containing circuitry for a plurality of individual semiconductor chips separated by scribe regions, said reticle having at least one die location containing a wafer test probe landing cite to receive test signals to test at least a group of said individual semiconductor chips, said wafer test probe landing cite wired to said individual semiconductor chips through at least one of said scribe regions so that said test signals are transported through said at least one of said scribe regions, wherein each one of said semiconductor chips is an RFID tag semiconductor chip, and wherein each one of said individual RFID tag semiconductor chips comprises a receive signal path from one or more inputs to a controller, said receive signal path to process an electrical receive signal originating from said input(s) as a consequence of said input(s) having received a wireless signal, a second signal path flowing into said receive signal path from a die edge, said second signal path to transport an electrical test signal provided by said wafer test probe landing site.

23. The apparatus of claim 22 wherein said receive signal path flows through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said second signal path.

24. The apparatus of claim 22 wherein each of said individual RFID tag semiconductor chips further comprise:

a rectifier coupled to said input(s), a node where a supply voltage for the RFID tag semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to supply voltage wiring that provides a supply voltage provided by said wafer test probe.

25. The apparatus of claim 24 wherein each of said RFID tag semiconductor chips further comprise:

a multiplexer to multiplex between test signals generated while said RFID tag semiconductor chip is being tested on wafer, said multiplexer having its power supply node coupled to said power supply wiring.

26. The semiconductor wafer of claim 22 wherein said at least one die location includes four die locations each reserved for a wafer test probe landing cite to receive respective test signals for at least a respective portion of said individual RFID tag semiconductor chips, each one of said four die locations residing in a corner of said reticle.