Configurable integrated circuit with built-in turns

• US 7,312,630 B2
• Filed: 06/30/2004
• Issued: 12/25/2007
• Est. Priority Date: 06/30/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US10/882,945
• Publication Number:
  US 20070241770A1
• Time in Patent Office: 1,273 Days
• Field of Search: 326 37- 41, 326/47, 326/101
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments provide a configurable integrated circuit (“IC”) with a configurable node array. A configurable node array may include configurable nodes arranged in rows and columns. It may also include direct offset connections, with each direct offset connection connecting two nodes that are neither in the same column nor the same row. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by a set of wire segments that traverse through a set of the IC'"'"'s wiring layers, and a set of vias when multiple wiring layers are involved. Some of the direct connections may have intervening circuits (e.g. buffer circuits). In some embodiments, the nodes in the array are all similar to each other.

Claims

1. An integrated circuit (“

IC”

) comprising;

a) at least fifty configurable nodes arranged in an array, said configurable nodes comprising;

i) a configurable first node;

ii) a configurable second node offset by a positional relationship from the configurable first node;

iii) a symmetrical subset of configurable nodes comprising a subset of configurable nodes in the array that are each offset from said configurable first node by a positional relationship that is symmetrical to the positional relationship that the configurable second node has with the configurable first node, wherein positional relationships are symmetrical when they are formed by symmetry about at least one of a vertical axis and a horizontal axis through the configurable first node; and

b) a set of wire segments directly connecting said configurable first node and said configurable second node;

c) said configurable first node is not directly connected to any nodes in said symmetrical subset of configurable nodes.

2. The IC of claim 1, wherein two nodes in an array are offset by a symmetrical positional relationship from a reference node if and only if:

a) one of the two nodes is offset from the reference node by M nodes in a vertical direction and N nodes in a horizontal direction, wherein M and N are integers; and

b) the other of the two nodes is offset from the reference node by;

i) plus M nodes in said vertical direction and minus N nodes in said horizontal direction;

ii) minus M nodes in said vertical direction and plus N nodes in said horizontal direction;

or

iii) minus M nodes in said vertical direction and minus N nodes in said horizontal direction.

3. The IC of claim 2, wherein said configurable second node is offset from said configurable first node by at least two nodes in a first direction and at least one node in a second direction.

4. The IC of claim 1, wherein two nodes are not directly connected if they are connected through at least one intervening interconnect circuit.

5. An integrated circuit (“

IC”

) comprising;

a) at least fifty configurable nodes arranged in an array;

b) a configurable first node in said array with an asymmetric set of direct connections, wherein a direct connection of a particular node is asymmetric if;

i) at least one direct connection connects the particular node to a second node, offset from the particular node in the array;

ii) the array includes a symmetrical set of nodes, wherein each node of said symmetrical set of nodes has a positional relationship with the particular node that is symmetrical to a positional relationship that the second node has with the particular node, wherein positional relationships are symmetrical when they are formed by symmetry about at least one of a vertical axis and a horizontal axis through the particular node; and

iii) no direct connections connect the particular node with the symmetrical set of nodes.

6. The integrated circuit of claim 5, wherein the asymmetric set of direct connections is an asymmetric first set of direct connections, said IC further comprising:

a configurable third node in said array with an asymmetric second set of direct connections that is a same shape, as the asymmetric first set of direct connections.

7. The integrated circuit of claim 6, wherein the asymmetric second set of direct connections is oriented at an angle relative to the asymmetric first set of direct connections.

8. The integrated circuit of claim 7, wherein said angle is approximately 90 degrees, approximately 180 degrees, or approximately 270 degrees.

9. The integrated circuit of claim 6, wherein the asymmetric second set of direct connections is a mirror image of the asymmetric first set of direct connections.

10. An integrated circuit (“

IC”

) comprising;

a) a plurality of configurable nodes in an arrangement, wherein each node comprises a configurable logic circuit; and

b) a plurality of direct connections each connecting a configurable logic circuit to a node other than its own;

c) wherein at least one direct connection connects an output of a configurable logic circuit to an offset node without using intervening interconnect circuits, wherein two configurable nodes are offset when they are not neighbors and are not vertically or horizontally aligned with each other.

11. The IC of claim 10, wherein a plurality of direct connections each connect an output of a configurable logic circuit to an offset node without using intervening interconnect circuits.

12. The IC of claim 10, wherein said at least one direct connection connects said output of said configurable logic circuit to a configurable logic circuit of said offset node.

13. The IC of claim 10, wherein said at least one direct connection connects said output of said configurable logic circuit to a configurable interconnect circuit of said offset node.

14. The IC of claim 10, wherein said at least one direct connection comprises a set of wire segments.

15. The IC of claim 10, wherein said at least one direct connection comprises a set of wire segments and at least one buffer.

16. The IC of claim 10, wherein said at least one direct connection comprises a set of wire segments and at least one via.