Methods and apparatus for improved memory access
First Claim
1. A method for accessing data from an input/out port while a shift register shifts according to shift clock signals, comprising:
- sampling a data signal from the input/output port before the shift register shifts in a shift input data signal;
holding the sampled data signal until after the shift register shifts in the shift input data signal;
shifting the shift input data signal into the shift register;
overwriting the shift input data signal with the sampled data signal before the shift register shifts out the shift input data signal; and
shifting the sampled data signal out of the shift register.
7 Assignments
0 Petitions
Accused Products
Abstract
A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.
-
Citations
16 Claims
-
1. A method for accessing data from an input/out port while a shift register shifts according to shift clock signals, comprising:
-
sampling a data signal from the input/output port before the shift register shifts in a shift input data signal; holding the sampled data signal until after the shift register shifts in the shift input data signal; shifting the shift input data signal into the shift register; overwriting the shift input data signal with the sampled data signal before the shift register shifts out the shift input data signal; and shifting the sampled data signal out of the shift register. - View Dependent Claims (2, 3, 4)
-
-
5. A method for accessing data from an input/output port while a shift register shifts according to shift clock signals, comprising:
-
shifting in a shift input data signal into the shift register; sampling a data signal from the input/output port at approximately the same time as the shift register shifts in the shift input data signal; holding the sampled data signal separate from the shift input data signal; overwriting the shift input data signal with the held, sampled data signal; removing the shift input signal at approximately the same time as overwriting begins; and shifting out the overwritten sampled data signal from the shift register at approximately the same time as overwriting begins. - View Dependent Claims (6, 7, 8)
-
-
9. An apparatus for accessing data from an input/out port while a shift register shifts according to shift clock signals, comprising:
-
means for sampling a data signal from the input/output port before the shift register shifts in a shift input data signal; means for holding the sampled data signal until after the shift register shifts in the shift input data signal; means for shifting the shift input data signal into the shift register; means for overwriting the shift input data signal with the sampled data signal before the shift register shifts out the shift input data signal; and means for shifting the sampled data signal out of the shift register. - View Dependent Claims (10, 11, 12)
-
-
13. An apparatus for accessing data from an input/output port while a shift register shifts according to shift clock signals, comprising:
-
means for shifting in a shift input data signal into the shift register; means for sampling a data signal from the input/output port at approximately the same time as the shift register shifts in the shift input data signal; means for holding the sampled data signal separate from the shift input data signal; means for overwriting the shift input data signal with the held, sampled data signal; means for removing the shift input signal at approximately the same time as overwriting begins; and means for shifting out the overwritten sampled data signal from the shift register at approximately the same time as overwriting begins. - View Dependent Claims (14, 15, 16)
-
Specification