Dynamic semiconductor storage device

• US 7,313,045 B2
• Filed: 04/13/2004
• Issued: 12/25/2007
• Est. Priority Date: 04/15/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hosokawa, Kohji, Miyatake, Hisatada, Sunaga, Toshio
• Primary Examiner(s): Yoha, Connie C.
• Application Number:
  US10/553,578
• Publication Number:
  US 20060250873A1
• Time in Patent Office: 1,351 Days
• Field of Search: 365/222, 365/225.7
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.

Claims

1. A dynamic semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of blocks;

a block decoder for decoding row address signals and producing block selection signals;

a refresh cycle control circuit, formed on the row decoder, for dividing the block selection signals by preset frequency dividing ratios to set refresh cycles for the blocks, the refresh cycle control circuit having a fuse circuit for setting the frequency dividing ratios and a frequency divider for dividing the block selection signals by frequency dividing ratios set in the fuse circuit; and

a row decoder for selecting the blocks in response to the block selection signals.

2. A method of selectively controlling a refresh cycle time of a dynamic semiconductor memory device, comprising:

dividing a memory cell array including a plurality of memory cells into a plurality of blocks;

decoding row address signals and a plurality of producing block selection signals;

dividing the block selection signals by preset frequency dividing ratios to set refresh cycles for the blocks using a refresh cycle control circuit;

selecting the blocks in response to the block selection signals with a row decoder;

setting the frequency dividing ratios with a fuse circuit;

dividing the block selection signals by frequency dividing ratios set in the fuse circuit using a frequency divider; and

forming the fuse circuit on the row decoder.