Method and apparatus for controlling scanning of mosaic sensor array

• US 7,313,053 B2
• Filed: 10/29/2004
• Issued: 12/25/2007
• Est. Priority Date: 03/06/2003
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Wodnicki, Robert Gideon
• Primary Examiner(s): Lobo; Ian J.
• Application Number:
  US10/978,012
• Publication Number:
  US 20050057284A1
• Time in Patent Office: 1,152 Days
• Field of Search: 367/153, 600/437, 600/443, 600/447
• US Class Current: 367/153
• CPC Class Codes: A61B 8/13 Tomography A61B8/10, A61B8/12 take precedence; tomography for radiation diagnosis A61B6/02
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B06B 1/0625 Annular array
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration

Abstract

A scanning architecture that makes it possible to update only those ultrasonic transducer subelements of a mosaic transducer array that change from view to view. The configuration of the switch matrix is fully programmable. The switch matrix includes access switches that connect subelements to bus lines and matrix switches that connect subelements to subelements. Each subelement has a unit switch cell associated therewith, each unit switch cell comprising at least one access switch, at least one matrix switch, and addressing and control logic. Optionally, each unit switch cell also includes latches for storing the future switch states of the switches to be programmed. The switches themselves have memory for storing their current switch states.

Claims

1. A device comprising:

a multiplicity of sensors arranged along generally parallel lines;

a multiplicity of bus lines,

a first multiplicity of switches for selectively electrically connecting sensors to bus lines, wherein each switch of said first multiplicity is of a type that can memorize data representing its current switch state, each sensor having at least a respective switch of said first multiplicity associated therewith;

a second multiplicity of switches for selectively electrically connecting sensors to each other, wherein each switch of said second multiplicity is of a type that can memorize data representing its current switch state, each sensor having at least a respective switch of said second multiplicity associated therewith;

data generator circuitry for generating switch state data representing the state of switches of said first and second multiplicities to be programmed;

address generator circuitry for generating address data identifying said switches of said first and second multiplicities to be programmed; and

a multiplicity of control logic circuits for outputting switch state control data to said switches of said first and second multiplicities to be programmed in response to receipt of said switch state data, each sensor having a respective control logic circuit associated therewith, said switch state control data controlling the state of said switches and being derived from said switch state data, and each sensor having a respective control logic circuit associated therewith.

2. The device as recited in claim 1, wherein each of said sensors comprises a respective ultrasonic transducer subelement.

3. The device as recited in claim 2, wherein each of said ultrasonic transducer subelements comprises a respective plurality of cMUT cells that are not switchably disconnectable from each other.

4. The device as recited in claim 2, wherein said ultrasonic transducer subelements are arranged in a hexagonal array, each ultrasonic transducer subelement having three switches of said second multiplicity associated therewith for respectively electrically connecting an ultrasonic transducer element with any of three neighboring ultrasonic transducer subelements.

5. The device as recited in claim 1, further comprising a view generator that programs said address and data generator circuitry to configure the first and second multiplicities of switches as required for a given view.

6. The device as recited in claim 1, further comprising a multiplicity of latches for storing said switch state data from said data generator circuitry during a first time period and then writing said switch state data into said control logic circuits during a second time period subsequent to said first time period.

7. The device as recited in claim 6, wherein said switch state control data memorized in said selected switches of said first and second multiplicities of switches represents a transmit aperture pattern, while said switch state data stored in said latches will be converted into switch state control data that represents a receive aperture pattern.

8. The device as recited in claim 1, wherein the switches identified during one cycle represent a first region of interest, while the switches identified during a subsequent cycle represent a second region of interest, but said second region of interest being shifted relative to said first region of interest.

9. The device as recited in claim 1, wherein the switch state control data memorized in a first set of switches of said first and second multiplicities during a predetermined time period represents a transmit aperture pattern, while the switch state control data memorized in a second set of switches of said first and second multiplicities during said predetermined time period represents a receive aperture pattern.

10. The device as recited in claim 1, further comprising a multiplicity of address/data bus lines for carrying said address data and said switch state data, and a multiplicity of multiplexers situated between said data and address generator circuitry and said address/data bus lines, said multiplexers connecting said address generator circuitry to said address/data bus lines in a first multiplexer state and connecting said data generator circuitry to said address/data bus lines in a second multiplexer state.

11. The device as recited in claim 6, further comprising:

means for connecting respective sets of said latches along an X direction to form respective X-direction shift registers;

a multiplicity of address/data bus lines respectively connected to said sets of latches;

a multiplicity of multiplexers situated between said data and address generator circuitry and said sets of address/data buses, said multiplexers connecting said address generator circuitry to said address/data buses in a first multiplexer state and connecting said data generator circuitry to said address/data buses in a second multiplexer state; and

X control means for controlling the shifting of switch state data in an X direction in selected latches.

12. The device as recited in claim 11, further comprising:

means for connecting respective sets of said latches along a Y direction to form respective Y-direction shift registers; and

Y control means for controlling the shifting of switch state data in a Y direction in selected latches.

13. The device as recited in claim 11, wherein the address data and the switch state data are selected to repair shift register lines that have inoperable elements.

14. The device as recited in claim 11, wherein selected latches are programmed by said address and data generator circuitry for a region of interest, and thereafter the switch state data in said selected latches is shifted by said X control means for shifting said region of interest.

15. The device as recited in claim 1, further comprising a multiplicity of data bus lines for electrically connecting said data generator circuitry to said control logic circuitry, and a multiplicity of column select lines for electrically connecting said address generator circuitry to said control logic circuitry, said multiplicity of data bus lines running generally parallel to said lines of sensors, and said column select lines being not parallel to said data bus lines.

16. The device as recited in claim 15, wherein said address generator circuitry comprises a first shift register loaded with a region of interest bit pattern that is shifted to move the block of columns that accept the switch state data from said data generator circuitry.

17. The device as recited in claim 16, wherein said address generator circuitry further comprises a second shift register that shifts a bit in round robin within the bounds of said region of interest to select columns in sequence for addressing.

18. The device as recited in claim 1, further comprising a multiplicity of address/data bus lines for carrying said address data and said switch state data from said address and data generator circuitry respectively, and a multiplicity of latches situated between said data and address generator circuitry and said address/data bus lines, one latch per address/bus line.

19. The device as recited in claim 1, wherein said data generator circuitry comprises a dedicated data generator for each line of sensors.

20. The device as recited in claim 1, wherein said data generator circuitry comprises an FPGA, a CPU or a digital ASIC which generates data algorithmically.

21. The device as recited in claim 1, wherein said data generator circuitry comprises a RAM, ROM, EPROM, EEPROM, MRAM, FRAM, or any other memory device for storing said switch state data coupled to an FPGA, CPU, or ASIC to direct readout of switch state data to the array.

22. The device as recited in claim 1, wherein said address generator circuitry and said data generator circuitry are respectively provided on both sides of said multiplicity of sensors and the switches of said first and second multiplicities associated with said lines of sensors are divided into right and left segments, the switches of said left segments being controlled by said address and data generator circuitry on one side, and the switches of said right segments being controlled by said address and data generator circuitry on the other side.

23. The device as recited in claim 15, wherein said address generator circuitry is provided above and below said multiplicity of sensors and the column select lines are divided into top and bottom segments, the switches of said first and second multiplicities connected to said top segments of said column select lines being addressed by said address generator circuitry on the top, and the switches of said first and second multiplicities connected to said bottom segments of said column select lines being addressed by said address generator circuitry on the bottom.

24. The device as recited in claim 1, further comprising a multiplicity of decoding circuits for decoding address data from said address generator circuitry, each sensor being associated with a respective decoding circuit.

25. The device as recited in claim 1, wherein each control logic circuit comprises a respective plurality of logic gates that output said switch state control data in response to a global strobe signal.

26. The device as recited in claim 6, further comprising a multiplicity of address/data bus lines for carrying said address data and said switch state data from said address and data generator circuitry respectively, wherein each of said latches is of a type wherein the switch state data stored therein can be read out to said address/data bus lines in response to a read command.

43. The device as recited in claim 11, wherein said X control means comprises first and second region of interest shifting controllers.

27. A device comprising:

a multiplicity of sensors arranged along generally parallel lines;

a multiplicity of bus lines, and

a multiplicity of unit switch cells, each unit switch cell being associated with a respective sensor and comprising;

(a) a first switch for connecting said associated sensor to a bus line, (b) a second switch for connecting said associated sensor to a neighboring sensor, and (c) a control logic circuit for outputting switch state control data to said first and second switches in response to receipt of switch state data representing the desired states of said first and second switches, said switch state control data controlling the state of said first and second switches and being derived from said switch state data, and each of said first and second switches being of a type that can memorize data representing its current switch state;

data generator circuitry for generating switch state data for selected first and second switches; and

address generator circuitry for generating address data identifying which of said first and second switches have been selected to be programmed.

28. The device as recited in claim 27, wherein each of said sensors comprises a respective ultrasonic transducer subelement.

29. The device as recited in claim 27, wherein each of said unit switch cells further comprises respective first and second latches for storing switch state data for said first and second switches during a first time period and then writing said switch state data into said control logic circuit during a second time period subsequent to said first time period.

30. The device as recited in claim 27, wherein each of said unit switch cells further comprises a decoding circuit for decoding address data from said address generator circuitry.

31. The device as recited in claim 29, wherein the first and second latches for unit switch cells associated with a line of sensors are connected to form a shift register.

32. The device as recited in claim 27, wherein each of said unit switch cells comprises means for storing multiple transmit or receive aperture switch settings locally within each cell and reading out the respective switch settings during transmit or receive beam formation to create multiple transmit or receive focal zones.

33. The device as recited in claim 32, wherein said storing means comprise more than one register for storage of multiple switch settings that can be read out during transmit or receive imaging.

34. The device as recited in claim 33, wherein said registers form a shift register with serial data read-out.

35. The device as recited in claim 33, wherein said registers form a random access memory with data read out selectively using random access.

36. A device comprising:

a multiplicity of sensors arranged along generally parallel lines;

a multiplicity of bus lines,

a first multiplicity of switches for selectively electrically connecting sensors to bus lines, wherein each switch of said first multiplicity is of a type that can memorize data representing its current switch state, each sensor having at least a respective switch of said first multiplicity associated therewith;

a second multiplicity of switches for selectively electrically connecting sensors to each other, wherein each switch of said second multiplicity is of a type that can memorize data representing its current switch state, each sensor having at least a respective switch of said second multiplicity associated therewith;

data generator circuitry for generating switch state data representing the state of switches of said first and second multiplicities to be programmed;

a multiplicity of latches for storing said switch state data from said data generator circuitry;

a multiplicity of data bus lines respectively connected to said sets of latches;

means for connecting respective sets of said latches along an X direction to form respective X-direction shift registers;

Y control means for controlling the shifting of switch state data in an Y direction in selected latches;

means for connecting respective sets of said latches along a Y direction to form respective Y-direction shift registers; and

X control means for controlling the starting point at which switch state data enters said sets of latches and controlling the shifting of switch state data in a X direction in selected latches.

37. A reconfigurable sensor array comprising:

(a) a multiplicity of sensors tiled over a two-dimensional area;

(b) a multiplicity of bus lines;

(c) a multiplicity of switches for connecting selected sensors to each other or connecting selected sensors to respective bus lines, wherein each of said switches comprises respective switch state memory, said switch state memories storing switch state control data representing the current states of said switches;

(d) a multiplicity of latches for storing switch state data representing the future states of said switches; and

(e) control logic for overwriting said switch state control data in the switch state memories of said switches with new switch state control data derived from said switch state data output from said latches.

38. The sensor array as recited in claim 37, wherein each of said sensors comprises a respective ultrasonic transducer subelement.

39. The sensor array as recited in claim 38, wherein each of said ultrasonic transducer subelements comprises a respective plurality of cMUT cells that are not switchably disconnectable from each other.

40. The sensor array as recited in claim 37, further comprising data generator circuitry for generating said switch state data and a multiplicity of data lines for carrying said switch state data from said data generator circuitry toward said latches.

41. The sensor array as recited in claim 40, further comprising address generator circuitry for generating address data that identifies selected switches to be programmed based on said switch state data.

42. The sensor array as recited in claim 41, wherein each of said components (a) through (e) are integrated into a substrate or lamination, while said data and address generator circuitry are not integrated into said substrate or lamination.