Programmable on chip regulators with bypass
First Claim
1. A multi-giga bit transceiver (MGT) system for converting between parallel data and serial data comprising:
- first MGT circuitry for performing a first MGT function;
second MGT circuitry for performing a second MGT function;
at least one regulated power source and at least one unregulated power source, both coupled to selectively provide regulated and unregulated power to the first and second MGT circuitry;
programmable logic for providing control signals to select and operatively couple the first and second MGT circuitry to one of the at least one regulated and unregulated power sources;
receiver serial-in-parallel-out circuitry (Rx SIPO); and
a selectable power regulator for the Rx SIPO circuitry.
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Accused Products
Abstract
A device and a method for processing high data rate serial data includes circuitry for recovering or generating a clock based with varying amounts of phase noise or jitter based upon a particular application. To achieve the foregoing, regulated and unregulated power are selectively provided to the circuitry for recovering a clock, to the circuitry for generating a transmission clock, and to any other circuitry having different tolerance levels for jitter and phase noise. Each power regulator comprises a current supply module and voltage regulator module. The current supply module provides one of a plurality of selectable output current levels into an output node of the regulator. The voltage regulator module having selectable voltage divider ratios at a first input of a comparator regulates an amount of current the device sinks from the output node to adjust the output voltage.
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Citations
19 Claims
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1. A multi-giga bit transceiver (MGT) system for converting between parallel data and serial data comprising:
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first MGT circuitry for performing a first MGT function; second MGT circuitry for performing a second MGT function; at least one regulated power source and at least one unregulated power source, both coupled to selectively provide regulated and unregulated power to the first and second MGT circuitry; programmable logic for providing control signals to select and operatively couple the first and second MGT circuitry to one of the at least one regulated and unregulated power sources; receiver serial-in-parallel-out circuitry (Rx SIPO); and a selectable power regulator for the Rx SIPO circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A power regulator within programmable logic device (PLD) coupled to a power supply comprising:
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a current mirror having a reference current stage and selectable current mirror stages for providing one of a plurality of current levels into an output node; a voltage regulator stage coupled to adjustably sink current from and source current to the output node to maintain a specified output voltage at the output node; wherein the output node of the current mirror is further coupled to at least one selectable switch to selectively provide regulated power to at least one of a transmit parallel-in-serial-out (Tx PISO) transmitter phase locked-loop (Tx PLL) and a receiver phase locked-loop (Rx PLL); wherein the voltage regulator stage further includes an amplifier and a voltage divider with selectable divider resistors to create selectable voltage divider ratios, the voltage divider coupled to an input of the amplifier; and wherein the voltage regulator stage is further coupled to receive a reference voltage from a reference circuit and control signals from logic within the PLD for selecting divider resistors to create a specified voltage divider ratio to compensate for variations in the reference voltage. - View Dependent Claims (14)
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15. A method within a high data rate transceiver for converting between parallel data and serial data and for providing regulated power and unregulated power, comprising:
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generating a transmitter clock and a receiver clock; converting parallel data into serial data according to the transmitter clock; converting serial data into parallel data according to the receiver clock; selectively providing regulated and unregulated power to circuitry for generating the transmitter and receiver clocks and to circuitry for converting the parallel data into serial data; and selecting between regulated power and unregulated power and generating corresponding control signals to circuitry for generating the transmitter and receiver clocks and circuitry for converting the parallel data into serial data. - View Dependent Claims (16, 17, 18, 19)
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Specification