Transceiver for receiving and transmitting data over a network and method for testing the same

• US 7,313,178 B2
• Filed: 04/10/2002
• Issued: 12/25/2007
• Est. Priority Date: 04/10/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Iadanza, Joseph A.
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): Vlahos; Sophia
• Application Number:
  US10/063,316
• Publication Number:
  US 20030193996A1
• Time in Patent Office: 2,085 Days
• Field of Search: 702/120, 702/69, 702/71, 702/72, 702/75, 702/78, 702/79, 702/106, 702/107, 702/122, 702124-126, 702/189, 702176-178, 714814-815, 714/724, 714/731, 714/819, 714/744, 714/715, 714/821, 714/733, 714/738, 714/739, 714/704, 714/703, 714/799, 714/30, 375224-227, 375/371, 375/219, 375/229, 375/221, 375/220, 375/222, 375/377, 375/213, 708/250, 708/252, 370/249, 370/366, 370/506, 370/214, 370/245
• US Class Current: 375/224
• CPC Class Codes: H04L 1/24 Testing correct operation

Abstract

The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, among other things, pulse density/width variation and jitter control.

Claims

1. A transceiver for receiving and transmitting data over a network, comprising:

a transmitter for receiving a network data signal representative of a signal capable of being transmitted over a network and a control signal for impairing characteristics of the network data signal, and for continuously generating an output signal corresponding to the data signal and the control signal during a predetermined time window;

a receiver for continuously receiving the output signal from the transmitter, and for reconstructing the network data signal within the predetermined time window; and

a built-in-self-test (BIST) device for generating the network data signal and the control signal, and for providing a reference clock signal with a varied offset for jitter testing the transceiver, wherein the BIST device detects erroneous performance by the transceiver based on the reconstructed network data signal;

wherein the BIST device includes a jitter control system comprising;

a multiplexor for outputting the reference clock signal;

at least one delay timer for delaying an input clock signal;

a shift register for controlling the multiplexor; and

a controller for controlling the multiplexor and updating the shift register.

2. The transceiver of claim 1, wherein the control signal includes signals for impairing a phase and an amplitude of the network data signal.

3. The transceiver of claim 1, wherein the jitter control system varies an offset of the reference clock signal.

4. The transceiver of claim 1, wherein the BIST device further comprises a pulse width counter for varying a pulse width of the network data signal.

5. The transceiver of claim 4, wherein the pulse width counter tests a clock recovery capability of the receiver.

6. A transceiver for receiving and transmitting data over a network, comprising:

a transmitter for receiving a network data signal representative of a signal capable of being transmitted over a network and a control signal for impairing characteristics of the network data signal, and for continuously generating an output signal corresponding to the data signal and the control signal during a predetermined time window;

a receiver for continuously receiving the output signal from the transmitter, and for reconstructing the network data signal within the predetermined time window; and

a built-in-self-test (BIST) device for generating the network data signal and the control signal, and for varying a pulse width of the network data signal and for varying an offset of a reference clock signal embedded within the network data signal, wherein the BIST device comprises means for detecting erroneous performance by the transceiver based on the reconstructed network data signal and the BIST device includes a jitter control system comprising;

a multiplexor for outputting the reference clock signal;

at least one delay timer for delaying an input clock signal;

a shift register for controlling the multiplexor; and

a controller for controlling the multiplexor and updating the shift register.

7. The transceiver of claim 6, wherein the control signal includes signals for impairing a phase and an amplitude of the network data signal.

8. The transceiver of claim 6, wherein the BIST device comprises means for programming the network data signals.

9. The transceiver of claim 6, wherein the transmitter and the receiver are provided on a single integrated circuit, the transceiver further comprising a transfer gate for selectively coupling the output signal from the transmitter to the receiver within the integrated circuit.

10. The transceiver of claim 6, wherein the network data signal includes an embedded reference clock signal, and wherein the BIST device comprises means for locking onto the embedded reference clock signal.

11. The transceiver of claim 10, wherein the means for detecting erroneous performance by the transceiver comprises a counter device for counting edge transitions of the reference clock signal for establishing a time window for reconstructing the network data signal data recovered from the output signal.

12. The transceiver of claim 11, wherein the means for detecting erroneous performance by the transceiver further comprises a counter device for counting edge transitions of the network data signal within the established time window.

13. A method for testing performance of a transceiver for receiving and transmitting data over a network, comprising the steps of:

generating a network data signal representative of signals capable of being transmitted over a network, and generating a control signal for impairing characteristics of the network data signal;

varying a pulse width of the network data signal;

varying an offset of a reference clock signal embedded within the network data signal;

a transmitter component of the transceiver device receiving the network data signal and the control signal and generating an output signal corresponding to the network data signal and having an impaired characteristic according to the control signal, the output signal being generated continuously during a predetermined time window;

a receiver component of the transceiver device continuously receiving the output signal from the transmitter component and reconstructing the network data signal within the predetermined time window; and

detecting erroneous performance by the transceiver based on the reconstructed data signal;

wherein the offset varying includes;

outputting a reference clock signal embedded within the network data signal;

delaying an input clock signal; and

controlling the reference clock signal outputting.

14. The method of claim 13, wherein the step of reconstructing the network data signal comprises counting edge transitions of the embedded reference clock signal to establish the predetermined time window.

15. The method of claim 13, wherein the step of reconstructing the network data signal comprises counting edge transitions of the network data signal within the predetermined time window.

16. A program product stored on a recordable medium for testing a transceiver device, which when executed, comprises:

program code for generating a network data signal representative of data capable of being transmitted over a network by a transceiver device and for generating a control signal for impairing characteristics of the network data signal;

program code for varying a pulse width of the network data signal;

program code for varying an offset of a reference clock signal embedded within the network data signal;

program code for enabling a transmitter component of the transceiver device to receive said network data signal and the control signal, and for generating an output signal corresponding to the network data signal having an impaired characteristic according to the control signal, wherein the output signal is generated continuously during a predetermined time window;

program code for enabling a receiver component of the transceiver device to continuously receive the output signal from the transmitter component and for reconstructing the network data signal within the predetermined time window; and

program code for detecting erroneous performance by the transceiver device based on the reconstructed network data signal;

wherein the offset varying program code controls a jitter control system comprising;

a multiplexor for outputting the reference clock signal;

at least one delay timer for delaying an input clock signal;

a shift register for controlling the multiplexor; and

a controller for controlling the multiplexor and updating the shift register.

17. The program product of claim 16, wherein the program code for reconstructing the network data signal comprises program code for counting edge transitions of the embedded reference clock signal to establish the predetermined time window.

18. The program product of claim 16, the program code for reconstructing the network data signal comprises program code for counting edge transitions of the network data signal within the predetermined time window.