DC offset correction for a wireless communication system

• US 7,313,376 B1
• Filed: 11/12/2004
• Issued: 12/25/2007
• Est. Priority Date: 11/12/2004
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Hietala, Alexander Wayne
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): Le, Nhan T.
• Application Number:
  US10/987,883
• Time in Patent Office: 1,138 Days
• Field of Search: 455/295, 455/296, 455/310, 455/312, 455/303, 455/307, 455/324, 455/340, 455/232.1, 455/234.1, 455/234.2, 455/239.1, 455/240.1, 455/250.1, 455/251.1, 455/255, 455/256, 455/313, 375/345
• US Class Current: 455/232.1
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A system and method for performing DC offset correction in a wireless communication receiver during “dead time” are provided. The receiver includes amplifier circuitry that amplifies a received radio frequency (RF) signal, downconversion circuitry that downconverts the received RF signal to provide a downconverted signal, digitization circuitry that digitizes the downconverted signal to provide a digital signal, and digital DC offset correction circuitry enabled during the dead time when there should be no DC content in the downconverted signal. In operation, the digital DC offset correction circuitry detects a DC offset of the digital signal and subtracts the DC offset from the digital signal.

Claims

1. A receiver for a wireless communication system comprising:

amplifier circuitry adapted to amplify a received radio frequency (RF) signal to provide an amplified RF signal;

downconversion circuitry adapted to convert the amplified RF signal to a downconverted signal;

digitization circuitry adapted to digitize the downconverted signal to provide a digital signal; and

digital DC offset correction circuitry adapted to receive the digital signal, detect a DC offset of the digital signal, and subtract the DC offset from the digital signal, wherein the digital DC offset correction circuitry is enabled during dead time when the downconverted signal should have no DC content and the amplifier circuitry is enabled.

2. The receiver of claim 1 wherein the digital DC offset correction circuitry comprises:

a digital low-pass filter adapted to filter the digital signal to detect the DC offset of the digital signal;

subtraction circuitry adapted to subtract the DC offset from the digital signal; and

timing circuitry adapted to enable the digital low-pass filter during dead time when the downconverted signal should have no DC content.

3. The receiver of claim 2 wherein the timing circuitry is further adapted to disable the digital low-pass filter at the end of the dead time, and the digital low-pass filter is further adapted to provide the DC offset of the digital signal as a constant value when disabled by the timing circuitry.

4. The receiver of claim 3 wherein the digital low-pass filter is further adapted to time average the DC offset of the digital signal and provide the DC offset to the subtraction circuitry upon being disabled by the timing circuitry.

5. The receiver of claim 2 wherein the receiver operates according to the Global System for Mobile Communications (GSM) standard.

6. The receiver of claim 5 wherein the dead time is at least a portion of a guard time defined by the GSM standard and corresponding to a period of time where the received RF signal contains guard bits, and the guard bits force a frequency of the downconverted signal to a fixed frequency offset from DC such that the fixed frequency is filtered from the digital signal by the digital low-pass filter.

7. The receiver of claim 6 wherein the timing circuitry is further adapted to disable the digital low-pass filter at a beginning of a first tail bit signifying an end of the guard time and a beginning of a received data burst.

8. The receiver of claim 6 wherein the guard time occurs between adjacent data bursts received by the receiver.

9. The receiver of claim 6 wherein the guard time occurs before a first data burst after the receiver is enabled.

10. The receiver of claim 1 wherein the receiver is a direct conversion receiver and the downconversion circuitry is further adapted to provide the downconverted signal at baseband.

19. The method of claim 1 wherein the guard time occurs before a first data burst after the receiver is enabled.

11. A method of performing DC offset correction in a receiver for a wireless communication system comprising:

amplifying a received radio frequency (RF) signal to provide an amplified RF signal;

downconverting the amplified RF signal to a downconverted signal;

digitizing the downconverted signal to provide a digital signal; and

detecting a DC offset of the digital signal, and subtracting the DC offset from the digital signal during a dead time when the downconverted signal should have no DC content and the amplified RF signal is provided by amplifying the received RF signal.

12. The method of claim 11 further comprising subtracting the DC offset from the digital signal.

13. The method of claim 12 wherein detecting the DC offset of the digital signal comprises low-pass filtering the digital signal to detect the DC offset of the digital signal.

14. The method of claim 13 further comprising disabling the low-pass filtering of the digital signal at the end of the dead time and providing the DC offset of the digital signal as a constant value when the low-pass filtering of the digital signal is disabled.

15. The method of claim 14 wherein the low-pass filtering of the digital signal comprises time averaging the DC offset of the digital signal.

16. The method of claim 15 wherein the receiver operates according to the Global System for Mobile Communications (GSM) standard, and detecting the DC offset of the digital signal during the dead time comprises detecting the DC offset of the digital signal during at least a portion of a guard time defined by the GSM standard and corresponding to a period of time where the received RF signal contains guard bits, wherein the guard bits force a frequency of the downconverted signal to a fixed frequency offset from DC such that low-pass filtering the digital signal removes the fixed frequency.

17. The method of claim 15 further comprising disabling the low-pass filtering of the digital signal at a beginning of a first tail bit signifying an end of the guard time and a beginning of a received data burst.

18. The method of claim 15 wherein the guard time occurs between adjacent data bursts received by the receiver.