GPS receiver having RF front end power management and simultaneous baseband searching of frequency and code chip offset

• US 7,313,421 B2
• Filed: 09/28/2004
• Issued: 12/25/2007
• Est. Priority Date: 09/28/2004
• Status: Expired due to Fees

• Current Assignee: G2 Microsystems Pty Limited
• Original Assignee: G2 Microsystems Pty Limited
• Inventors: Dejanovic, Thomas, Single, Peter S., Adams, Andrew
• Primary Examiner(s): Nguyen, Lee
• Application Number:
  US10/952,967
• Publication Number:
  US 20060068853A1
• Time in Patent Office: 1,183 Days
• Field of Search: 455/574, 455/343.1, 455/456.1, 342/357.12, 375/134, 375/137
• US Class Current: 455/574
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: H04B 1/1607 Supply circuits converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46

Abstract

A GPS receiver includes baseband resources for simultaneous determination of carrier frequency shift and code chip offset. Reduction in the power consumption of a receiver is achieved by managing the sampling rate of an analog-to-digital converter, the intermediate frequency of the RF front end, and the front end bandwidth so these are appropriate to the current function of the receiver. In a GPS receiver during signal tracking, the IF, front end bandwidth, and ADC sampling rate are set as high as possible; during signal acquisition, the IF and front end bandwidth are set to relatively low values, and the ADC sample rate is set to a high value; and during ephemeris download, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values. When a low battery condition is detected, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values regardless of whether the GPS receiver is in the signal acquisition mode, signal tracking mode, or ephemeris download mode.

Claims

1. A GPS receiver, comprising:

an RF front end including an IF stage and an analog-to-digital converter;

a digital baseband processor coupled to receive a digital baseband signal from the analog-to-digital converter of the RF front end; and

control circuitry coupled to the RF front end and the digital baseband processor,

wherein a frequency of the IF stage is operable to be increased or decreased responsive to the control circuitry, a sample rate of the analog-to-digital converter is operable to be increased or decreased responsive to the control circuitry, and a bandwidth of the RF front end is operable to be increased or decreased responsive to the control circuitry, and

wherein during a signal acquisition mode the control circuitry sets the RF front end bandwidth to approximately 2 MHz, the intermediate frequency to approximately 3 MHz, and the ADC sample rate to greater than 10 MHz;

during an ephemeris download mode the control circuitry sets the RF front end bandwidth to approximately 2 MHz, the intermediate frequency to approximately 8 MHz, and the ADC sample rate to approximately 2 MHz.

2. A method of operating a GPS receiver having a front end, and a digital baseband processor, the front end including an IF (Intermediate Frequency) stage and an ADC (Analog to Digital Converter), the method comprising:

setting, if in a signal tracking mode, a front end bandwidth to a first value, an IF frequency to a second value, and an ADC sample rate to a third value;

setting, if in a signal acquisition mode, a front end bandwidth to a fourth value, an IF frequency to a fifth value, and an ADC sample rate to a sixth value; and

setting, if in an ephemeris download mode, a front end bandwidth to a seventh value, an IF frequency to an eighth value, and an ADC sample rate to a ninth value.

3. The method of claim 2, wherein the first value represents a front end bandwidth that is at or near the highest possible bandwidth of the front end, and the second value is approximately 8 MHz.

4. The method of claim 2, wherein the fourth value is approximately 2 MHz, the fifth value is approximately 3 MHz, and the sixth value is greater than approximately 10 MHz.

5. The method of claim 4, wherein the seventh value is approximately 2 MHz, the eighth value is approximately 3 MHz, and the ninth value is approximately 2 MHz.

6. The method of claim 2, setting an IF frequency comprises changing a local oscillator output frequency that is coupled to a mixer.

7. The method of claim 6, wherein the local oscillator comprises two or more fixed frequency oscillators and selection circuitry coupled thereto to select an output of one of the two or more fixed frequency oscillators, and further comprising powering down the non-selected fixed frequency oscillators.

8. The method of claim 2, further comprising:

determining whether a low battery condition exists; and

setting, if the determination is affirmative, the front end bandwidth to approximately 2 MHz, the IF to approximately 3 MHz, and the ADC sample rate to approximately 2 MHz, regardless of whether the GPS receiver is in signal acquisition mode, signal tracking mode, or ephemeris download mode.

9. The method of claim 2, further comprising:

simultaneously searching for carrier frequency shift and code chip offset.

10. The method of claim 9, wherein simultaneously searching for carrier frequency shift and code chip offset comprises simultaneously multiplying a digitized baseband signal by a plurality of digitally synthesized frequencies, each of the plurality of digitally synthesized frequencies being different from each other;

and concurrently with the multiplying, integrating the result of each multiplication.

11. A GPS receiver comprising:

a front end including an IF (Intermediate Frequency) stage and an ADC (Analog to Digital Converter); and

a digital baseband processor coupled to the front end to control the front end bandwidth, the IF frequency and the ACD sample rate;

wherein the digital baseband processor;

sets, if in a signal tracking mode, a front end bandwidth to a first value, an IF frequency to a second value, and an ADC sample rate to a third value;

sets, if in a signal acquisition mode, a front end bandwidth to a fourth value, an IF frequency to a fifth value, and an ADC sample rate to a sixth value; and

sets, if in an ephemeris download mode, a front end bandwidth to a seventh value, an IF frequency to an eighth value, and an ADC sample rate to a ninth value.

12. The receiver of claim 11, wherein the IF stage comprises a local oscillator and a mixer and wherein setting an IF frequency comprises changing the output frequency of the local oscillator.

13. The receiver of claim 12, wherein the local oscillator comprises two or more fixed frequency oscillators coupled to the mixer and selection circuitry coupled thereto and wherein the digital baseband processor selects an output of one of the two or more fixed frequency oscillators, and powers down the non-selected fixed frequency oscillators.

14. The receiver of claim 11, wherein the digital baseband processor further:

determines whether a low battery condition exists; and

sets, if the determination is affirmative, the front end bandwidth to approximately 2 MHz, the IF to approximately 3 MHz, and the ADC sample rate to approximately 2 MHz, regardless of whether the GPS receiver is in signal acquisition mode, signal tracking mode, or ephemeris download mode.

15. The receiver of claim 11, further comprising circuitry for determining the state of a battery, and communicating the battery state.