Test apparatus and test method for testing a device under test

• US 7,313,496 B2
• Filed: 02/11/2005
• Issued: 12/25/2007
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Ishida, Masahiro, Yamaguchi, Takahiro, Soma, Mani
• Primary Examiner(s): Barlow, John
• Assistant Examiner(s): SIEVERS, LISA C
• Application Number:
  US11/056,330
• Publication Number:
  US 20060184332A1
• Time in Patent Office: 1,047 Days
• Field of Search: 702/111
• US Class Current: 702/111
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back

Abstract

A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.

Claims

1. A testing apparatus for performing a testing on a device under test (DUT) comprising:

a performance board on which the DUT is mounted;

a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT on the basis of an output signal output by the DUT;

a pin electronics which is provided between said main frame and said performance board and performs sending and receiving signals between said main frame and the DUT;

a deterministic jitter injecting unit for receiving the output signal without passing through said pin electronics and a comparator, and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through said pin electronics and a driver; and

a switching unit for determining whether the input pin of the DUT is provided with the test signal output by said pin electronics or the loop signal output by said deterministic jitter injecting unit.

2. A testing apparatus as claimed in claim 1, wherein

said pin electronics comprises a driver for outputting the test signal to the input pin of the DUT and a comparator for receiving the output signal from an output pin of the DUT, and

said deterministic jitter injecting unit receives the output signal from the output pin without passing through said comparator of said pin electronics and inputs the loop signal to the input pin without passing through said driver of said pin electronics.

3. A testing apparatus as claimed in claim 1, wherein said pin electronics comprises

a first pin card which corresponds to the input pin of the DUT and provides the input pin of the DUT with the test signal generated by said main frame;

and

a second pin card which corresponds to the output pin of the DUT and receives the output signal output by the DUT, and

said switching unit further comprises,

a first switching unit which corresponds to the input pin and determines whether the input pin is connected to said first pin card or said deterministic jitter injecting unit; and

a second switching unit which corresponds to the output pin and determines whether the output pin is connected to said second pin card or said deterministic jitter injecting unit.

4. A testing apparatus as claimed in claim 3, wherein said switching unit and said deterministic jitter injecting unit are provided on a switch board provided between said performance board and said pin electronics.

5. A testing apparatus as claimed in claim 3, wherein said deterministic jitter injecting unit comprises a cable through which the output signal passes and which injects the deterministic jitter into the output signal.

6. A testing apparatus as claimed in claim 5, wherein said deterministic jitter injecting unit further comprises a limiting amplifier for removing an amplitude degrading component from the loop signal into which the deterministic jitter is injected and providing the input pin with the loop signal.

7. A testing apparatus as claimed in claim 5, further comprising a jitter amount control unit for controlling an amount of the deterministic jitter, which is injected into the output signal by said deterministic jitter injecting unit, by controlling the length of said cable through which the output signal passes.

8. A testing apparatus as claimed in claim 5, further comprising a jitter amount control unit for controlling an amount of the deterministic jitter, which is injected into the output signal by said deterministic jitter injecting unit, by controlling a response characteristic of a first-order filter.

9. A testing apparatus as claimed in claim 3, wherein said deterministic jitter injecting unit comprises a first-order filter through which the output signal passes and which injects the deterministic jitter into the output signal.

10. A testing apparatus as claimed in claim 9, wherein said deterministic jitter injecting unit further comprises a limiting amplifier for removing an amplitude degrading component from the loop signal into which the deterministic jitter is injected and providing the input pin with the loop signal.

11. A testing apparatus as claimed in claim 9, further comprising a jitter amount control unit for controlling an amount of the deterministic jitter, which is injected into the output signal by said deterministic jitter injecting unit, by controlling a response characteristic of said first-order filter.

12. A testing apparatus as claimed in claim 3, further comprising a jitter amount control unit for controlling an amount of the deterministic jitter, which is injected into the output signal by said deterministic jitter injecting unit, by controlling a pattern of the output signal output by the DUT.

13. A testing apparatus as claimed in claim 12, wherein said main frame provides the DUT with a control signal for outputting the output signal of a predetermined pattern to the DUT in case of performing the jitter testing.

14. A testing apparatus as claimed in claim 12, further comprising a jitter measuring unit for measuring a jitter of at least of the loop signal and the output signal in case of performing the jitter testing.

15. A testing apparatus as claimed in claim 3, further comprising a switch control unit for connecting the input pin and said first pin card to said first switch and the output pin and said second pin card to said second switch in case of performing a logic testing on the DUT, and connecting the input pin and said deterministic jitter injecting unit to said first switch and the output pin and said deterministic jitter injecting unit to said second switch in case of performing a jitter testing on the DUT.

16. A testing apparatus as claimed in claim 15, wherein said switch control unit controls said first switch via said first pin card and controls said second switch via said second pin card.

17. A testing apparatus as claimed in claim 1, further comprising a jitter measuring unit for measuring a jitter of at least of the loop signal and the output signal in case of performing the jitter testing.

18. A testing apparatus as claimed in claim 17, wherein said jitter measuring unit calculates a jitter injected by a signal transmission path other than said deterministic jitter injecting unit on the basis of a pattern of the output signal and corrects the measured jitter value.

19. A testing apparatus as claimed in claim 18, wherein means for injecting a sinusoidal jitter injects the sinusoidal jitter having a plurality of different frequency components into the test signal.

20. A testing apparatus as claimed in claim 1, wherein said main frame comprises a means for injecting a sinusoidal jitter into the test signal.

21. A testing method for performing a jitter testing on a device under test (DUT) by using a testing apparatus comprising a performance board on which the DUT is mounted;

a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT on the basis of an output signal output by the DUT;

a pin electronics which is provided between said main frame and said performance board and performs sending and receiving signals between said main frame and the DUT; and

a switching unit for determining whether or not said pin electronics is connected to the DUT, comprising;

a switch control step of making said switching unit disconnect said pin electronics and the DUT; and

a deterministic jitter injecting step of receiving the output signal without passing through said pin electronics and a comparator, and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through said pin electronics and a driver.