Memory arrangement in a computer system

• US 7,313,732 B2
• Filed: 07/30/2004
• Issued: 12/25/2007
• Est. Priority Date: 07/31/2003
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Perner, Martin
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US10/902,160
• Publication Number:
  US 20050028040A1
• Time in Patent Office: 1,243 Days
• Field of Search: 714/42, 714/54, 714/5
• US Class Current: 714/42
• CPC Class Codes: G06F 11/2294 by remote test

Abstract

A memory arrangement in a computer system can have at least one memory module with semiconductor components, which are arranged on the memory module, can be operated in parallel and are additionally connected to one another via a serial line. The memory arrangement can have an interface bus for driving the semiconductor components on a module-specific basis, and an interface, which is driven by a memory controller assigned to the memory module via the interface bus and accesses the semiconductor components via the serial line. During normal operation, it is possible to test and adjust the semiconductor components in proximity to the application and on a chip-specific basis via the interface.

Claims

1. A memory arrangement, comprising:

at least one memory module with semiconductor components operating in parallel and being connected to one another via a serial line;

an interface bus for driving the semiconductor components on a module-specific basis; and

an interface driven by a memory controller, assigned to the memory module via the interface bus, the interface coupled to the semiconductor components via the serial line for access, wherein, during normal operation, the interface tests and adjusts the semiconductor components by sending signals to the semiconductor components via the serial line.

2. The memory arrangement according to claim 1, further comprising:

a test system connected to the computer system via a remote connection to test and adjust the semiconductor components via the interface.

3. The memory arrangement according to claim 2, wherein the remote connection is a LAN or WAN connection.

4. The memory arrangement according to claim 1, wherein the interface comprises a circuit arrangement for converting an input code applied to the interface into serial signals which are passed via the serial line through the semiconductor components connected to the serial line and for receiving a result signal.

5. The memory arrangement according to claim 4, wherein the serial signals initiate parameter requesting, configuration, and/or adjustment of an operating mode of the semiconductor components in order to ascertain and output the result signals.

6. The memory arrangement according to claim 4, wherein the circuit arrangement is an ASIC.

7. The memory arrangement according to claim 4, wherein the circuit arrangement stores the result signals which have been ascertained and/or forwards them to the memory controller.

8. The memory arrangement according to claim 4, wherein each semiconductor component comprises an associated flexibly programmable test unit, the test unit, on the basis of the serial signals supplied to the semiconductor component via the serial connection, transmitting test modes for ascertaining test data on the semiconductor component, processing the test data, using the test data for further boot and/or test operations during normal operation in order to adjust the semiconductor component in proximity to application, and forwarding the test data as result signals to the interface for output.

9. The memory arrangement according to claim 4, wherein the test unit in the semiconductor components is programmable via the interface.

10. The memory arrangement according to claim 1, further comprising:

at least one further memory module with semiconductor components operated in parallel and connected to one another via a serial line, the semiconductor components of the memory module and the semiconductor components of the at least one further memory module being driven in parallel via the serial lines.

11. The memory arrangement according to claim 1, further comprising:

at least one further memory module, wherein the serial line is looped through the at least one further memory module such that the semiconductor components on the memory module and on the at least one further memory module are connected to one another in series.

12. The memory arrangement according to claim 1, wherein the interface is integrated in the memory controller and the memory controller is connected directly to the serial line that connects the semiconductor components on the memory module.

13. The memory arrangement according to claim 1, wherein the interface comprises an interface card supported by the memory controller.

14. The memory arrangement according to claim 9, wherein the test unit is programmed with firmware or function tests.

15. A memory device, comprising:

at least one memory module with semiconductor components mounted thereon and operating in parallel;

an interface bus coupling the semiconductor components in parallel to a memory controller for driving the semiconductor components in parallel during normal operation of the memory device;

a serial line interconnecting the semiconductor components in series; and

an interface configured to send a serial signal to the semiconductor components via the serial line, the serial signal being forwarded from one semiconductor component to a next semiconductor component in sequence, wherein the serial signal causes at least one of the semiconductor components to output operational information, perform a test, or make operational adjustments.

16. The memory device of claim 15, wherein the serial signal is supplied to the semiconductor components during normal operation of the memory device.

17. The memory device of claim 15, wherein the serial line is unidirectional and the interface is coupled to the serial line at a point before a first of the semiconductor components in a series and at a point after a last of the semiconductor components in the series.

18. The memory device of claim 17, wherein the semiconductor components supply data to the interface by appending the data to the serial signal.

19. The memory device of claim 15, wherein the at least one memory module comprises a plurality of memory modules, and the semiconductor components of at least two of the memory modules are serially interconnected via the serial line.

20. The memory device of claim 15, wherein the at least one memory module comprises a plurality of memory modules, and the memory device comprises a plurality of serial lines respectively corresponding to the memory modules, wherein an individual serial line serially interconnects the interface and the semiconductor components of an individual memory module.

21. The memory device of claim 15, wherein the interface is capable of controlling semiconductor components on an individual basis via the sePal signal.

22. The memory device of claim 15, wherein the memory controller supplies an input signal to the interface and the interface converts the input signal into the serial signal for transmission to the semiconductor components via the serial line.