Method and apparatus for synchronization of shared memory in a multiprocessor system

• US 7,313,794 B1
• Filed: 01/30/2003
• Issued: 12/25/2007
• Est. Priority Date: 01/30/2003
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ansari, Ahmad R.
• Primary Examiner(s): An; Meng-Al T.
• Assistant Examiner(s): Truong; Camquy
• Application Number:
  US10/354,813
• Time in Patent Office: 1,790 Days
• Field of Search: 718/104, 718/102, 710/241, 710/108
• US Class Current: 718/102
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

Method and apparatus for synchronizing access to a memory shared among a plurality of processors is described. In one example, each of the plurality of processors includes a primary bus for communicating with the memory and a secondary bus. A synchronization block is coupled to the secondary bus of each of the plurality of processors. The synchronization block includes at least one semaphore for controlling access among the plurality of processors to at least one data segment stored within the memory.

Claims

1. An apparatus for synchronizing access to a memory shared among a plurality of processors, each of the plurality of processors having a primary bus for communicating with the memory and a secondary bus, the apparatus comprising:

a synchronization block coupled to the secondary bus of each of the plurality of processors, at least a portion of the plurality of processors not capable of supporting a read-modify-write single instruction to the memory, the synchronization block having at least one semaphore for controlling access among the plurality of processors to at least one data segment stored within the memory;

the at least one semaphore being configured to control access among the plurality of processors to the at least one data segment stored within the memory;

the plurality of processors coupled between the synchronization block and the memory;

wherein access to and from the at least one semaphore by the plurality of processors is via the secondary bus and access to and from the memory by the plurality of processors is via the primary bus, the synchronization block, the plurality of processors, and the memory being coupled in series wherein traffic for the secondary bus does not contribute to traffic on the primary bus;

wherein the at least one semaphore comprises a plurality of registers, each of the plurality of registers having a set terminal, a clear terminal and an output terminal and an arbitration circuit coupled to the set terminal and the output terminal of each of the plurality of registers;

wherein the synchronization block further comprises a plurality of controllers, each of the plurality of controllers respectively coupled to the secondary bus, the clear terminal and the arbitration circuit; and

wherein each of the plurality of controllers comprises a decoder to provide read requests to the arbitration circuit and write requests to the clear terminal of a respective one of the plurality of registers in response to instructions from a respective one of the plurality of processors.

2. The apparatus of claim 1, wherein the arbitration circuit controllably sets one of the plurality of registers in at least partial response to a read request provided by one of the plurality of processors.

3. The apparatus of claim 1, wherein the arbitration circuit includes queuing logic for queuing read requests provided by the plurality of processors.

4. The apparatus of claim 1, wherein the secondary bus of each of the plurality of processors is a device control register bus.

5. A data processing system, comprising:

a plurality of processors, each of the plurality of processors including a primary bus and a secondary bus, at least a portion of the plurality of processors not capable of supporting a read-modify-write single instruction to memory;

the memory coupled to the primary bus of each of the plurality of processors;

a synchronization block coupled to the secondary bus of each of the plurality of processors, the synchronization block having at least one semaphore for controlling access among the plurality of processors to the memory; and

the plurality of processors coupled between the synchronization block and the memory;

wherein access to and from the at least one semaphore by the plurality of processors is via the secondary bus and access to and from the memory by the plurality of processors is via the primary bus, the synchronization block, the plurality of processors, and the memory being coupled in series wherein traffic for the secondary bus does not contribute to traffic on the primary bus;

wherein the at least one semaphore comprises a plurality of registers, each of the plurality of registers having a set terminal, a clear terminal and an output terminal and an arbitration circuit coupled to the set terminal and the output terminal of each of the plurality of registers;

wherein the synchronization block further comprises a plurality of controllers, each of the plurality of controllers respectively coupled to the secondary bus, the clear terminal and the arbitration circuit; and

wherein each of the plurality of controllers comprises a decoder to provide read requests to the arbitration circuit and write requests to the clear terminal of a respective one of the plurality of registers in response to instructions from a respective one of the plurality of processors.

6. The data processing system of claim 5, wherein the arbitration circuit controllably sets one of the plurality of registers in at least partial response to a read request provided by one of the plurality of processors.

7. The data processing system of claim 5, wherein the arbitration circuit includes queuing logic for queuing read requests provided by the plurality of processors.

8. The data processing system of claim 5, wherein the secondary bus of each of the plurality of processors is a device control register bus.

9. The data processing system of claim 5, wherein the plurality of processors are embedded within a programmable logic device.

10. The data processing system of claim 9, wherein the synchronization block is formed with programmed configurable logic blocks within the programmable logic device.

11. The data processing system of claim 5, wherein the at least one semaphore controls access among the plurality of processors at least one data segment stored within the memory.

12. A method of synchronizing access to a memory shared among a plurality of processors, each of the plurality of processors having a primary bus for communicating with the memory and a secondary bus, the method comprising:

providing at least one semaphore;

providing access to the at least one semaphore via the secondary bus of each of the plurality of processors;

determining a state of the at least one semaphore;

controlling access among the plurality of processors to at least one data segment stored within the memory in response to the state of the at least one semaphore, at least a portion of the plurality of processors not capable of supporting a read-modify-write single instruction to the memory;

the at least one semaphore being configured to control access among the plurality of processors to the at least one data segment stored within the memory; and

the plurality of processors coupled between a synchronization block in which the at least one semaphore is located and the memory;

wherein access to and from the at least one semaphore by the plurality of processors is via the secondary bus and access to and from the memory by the plurality of processors is via the primary bus, the synchronization block, the plurality of processors, and the memory being coupled in series wherein traffic for the secondary bus does not contribute to traffic on the primary bus;

wherein the at least one semaphore comprises a plurality of registers, each of the plurality of registers having a set terminal, a clear terminal and an output terminal and an arbitration circuit coupled to the set terminal and the output terminal of each of the plurality of registers;

wherein controlling access comprises allowing one of the plurality of processors to access the at least one data segment if the state of the at least one semaphore is a first value and blocking access by others of the plurality of processors to the at least one data segment if the state of the at least one semaphore is a second value

wherein the synchronization block further comprises a plurality of controllers, each of the plurality of controllers respectively coupled to the secondary bus, the clear terminal and the arbitration circuit; and

wherein each of the plurality of controllers comprises a decoder to provide read requests to the arbitration circuit and write requests to the clear terminal of a respective one of the plurality of registers in response to instructions from a respective one of the plurality of processors.

13. The method of claim 12, wherein the step of determining the state comprises reading the state of the at least one semaphore into a register within one of the plurality of processors.

14. A method of synchronizing access to a memory shared among a plurality of processors, each of the plurality of processors having a primary bus and a secondary bus, the primary bus for communicating with the memory, the method comprising:

providing a semaphore, the semaphore comprising a plurality of registers, each of the plurality of resisters having a set terminal, a clear terminal and an output terminal and an arbitration circuit coupled to the set terminal and the output terminal of each of the plurality of registers;

reading a state of the semaphore via the secondary bus by one of the plurality of processors;

locking shared data stored in the memory by blocking access to at least one address range associated with the shared data stored in the memory to others of the plurality of processors if the state of the semaphore indicates the memory is not locked;

the plurality of processors coupled between a synchronization block in which the semaphore is located and the memory, at least a portion of the plurality of processors not capable of supporting a read-modify-write single instruction to the memory;

wherein access to and from the semaphore by the plurality of processors is via the secondary bus and access to and from the memory by the plurality of processors is via the primary bus, the synchronization block, the plurality of processors, and the memory being coupled in series wherein traffic for the secondary bus does not contribute to traffic on the primary bus;

wherein the synchronization block further comprises a plurality of controllers, each of the plurality of controllers respectively coupled to the secondary bus, the clear terminal and the arbitration circuit; and

wherein each of the plurality of controllers comprises a decoder to provide read requests to the arbitration circuit and write requests to the clear terminal of a respective one of the plurality of registers in response to instructions from a respective one of the plurality of processors.

15. The method of claim 14, further comprising repeating the step of reading if the state of the semaphore indicates the memory is locked.

16. The method of claim 14, wherein the step of reading the state comprises:

transmitting a read request to the semaphore;

receiving a first value of the state of the semaphore that indicates the memory is locked;

re-transmitting the read request to the semaphore; and

receiving a second value of the state of the semaphore that indicates the memory is unlocked.

17. The method of claim 14, wherein the step of reading the state comprises;

transmitting a read request to the semaphore; and

receiving a value of the state of the semaphore that indicates the memory is unlocked.

18. The method of claim 17, wherein the step of reading is repeated if the read request times out.

19. The method of claim 14, further comprising:

accessing the memory via the primary bus by the one of the plurality of processors; and

unlocking the memory by allowing access to the memory to the others of the plurality of processors.

20. The method of claim 19, wherein the step of unlocking comprises:

transmitting a write request to the semaphore; and

storing a value in the semaphore indicating the memory is unlocked.

21. The method of claim 14, further comprising causing the one of the plurality of processors to be in a wait condition if the state of the semaphore indicates the memory is locked.

22. The method of claim 21, wherein the step of reading the state comprises:

transmitting a read request to the semaphore;

receiving a first value of the state of the semaphore that indicates the memory is locked; and

receiving a second value of the state of the semaphore that Indicates the memory is unlocked.

23. The method of claim 21, wherein the step of reading the state comprises;

transmitting a read request to the semaphore; and

receiving a value of the state of the semaphore that indicates the memory is unlocked.

24. The method of claim 23, wherein the one of the plurality of processors enters the wait condition if the read request times out.

25. The method of claim 21, further comprising causing the one of the plurality of processors to exit the wait condition if the state of the semaphore indicates the memory is unlocked.

26. The method of claim 21, further comprising:

accessing the memory via the primary bus of the one of the plurality of processors; and

unlocking the memory by allowing access to the memory by others of the plurality of processors.

27. The method of claim 26, wherein the step of unlocking comprises;

transmitting a write request to the semaphore; and

storing a value in the semaphore indicating the memory is unlocked.