Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification

• US 7,314,789 B2
• Filed: 12/30/2006
• Issued: 01/01/2008
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Liu, Xiao H., Kanarsky, Thomas S., Doris, Bruce B., Zhu, Huilong, Cabral, Cyril Jr.
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): Ahmadi; Mohsen
• Application Number:
  US11/618,751
• Publication Number:
  US 20070111421A1
• Time in Patent Office: 367 Days
• Field of Search: 438/197, 438/199, 438153-154, 438/157, 438/510, 257/369, 257/388, 257/E21.634, 257E21636-637, 257/E21.703
• US Class Current: 438/197
• CPC Class Codes: H01L 21/3215 Doping the layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

Claims

1. A method of forming a semiconductor structure having a local mechanical gate stress comprising the steps of:

providing a semiconductor structure having layers of a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a hard mask located on a surface of a semiconductor substrate, said semiconductor substrate containing a trench isolation region;

patterning said layers to provide at least one patterned gate stack for a NFET and a least one patterned gate stack for a PFET, said NFET and PFET are separated by said trench isolation region;

forming at least one spacer on sidewalls of each patterned gate stack and forming silicided source/drain regions in said semiconductor substrate adjacent each patterned gate stack;

forming a planarized dielectric film that exposes a top surface of each patterned gate stack;

selectively forming a silicide or a tensile metal in said at least one patterned gate stack for said PFET; and

selectively forming a compressive metal in said at least one patterned gate stack for said NFET.

2. The method of claim 1 further comprising selectively implanting dopants of a first conductivity type into a portion of the first gate electrode layer and selectively implanting dopants of a second conductivity dopant type, which differs from the first conductivity type, into another portion of the first gate electrode layer, wherein said both implanting steps are performed prior to patterning.

3. The method of claim 1 wherein said selectively forming a silicide comprises forming a hard mask over said NFET, forming a metal over exposed areas including said PFET, and performing a silicide annealing step.

4. The method of claim 1 wherein said selectively forming a tensile metal comprises forming a hard mask over said NFET, removing exposed portions of the Si-containing second gate electrode layer in said PFET, and depositing said tensile metal in the area previously containing the Si-containing second gate electrode layer.

5. The method of claim 1 wherein said selectively forming a compressive metal comprises forming a hard mask over said PFET, removing exposed portions of the Si-containing second gate electrode layer in said NFET, and depositing said compressive metal in the area previously containing the Si-containing second gate electrode layer.

6. The method of claim 1 wherein said tensile metal comprises Ta.

7. The method of claim 1 wherein said compressive metal comprises Ta.

8. The method of claim 1 wherein said compressive metal is sputtered deposited at a low pressure and a high substrate bias.

9. The method of claim 1 wherein said tensile metal is sputtered deposited at a high pressure and at no substrate bias.

10. A method of forming a semiconductor structure having a local mechanical gate stress comprising the steps of:

providing a semiconductor structure having layers of a gate dielectric, a first gate electrode layer, a barrier layer, a second gate electrode layer and a hard mask located on a surface of a semiconductor substrate, said semiconductor substrate containing a trench isolation region and said second gate electrode layer comprising a tensile metal or a silicide;

patterning said layers to provide at least one patterned gate stack for a NFET and a least one patterned gate stack for a PFET, said NFET and PFET are separated by said trench isolation region;

forming at least one spacer on sidewalls of each patterned gate stack and forming silicided source/drain regions in said semiconductor substrate adjacent each patterned gate stack;

forming a planarized dielectric film that exposes a top surface of each patterned gate stack; and

selectively forming a compressive metal in said at least one patterned gate stack for said NFET.

11. The method of claim 10 further comprising selectively implanting dopants of a first conductivity type into a portion of the first gate electrode layer and selectively implanting dopants of a second conductivity dopant type, which differs from the first conductivity type, into another portion of the first gate electrode layer, wherein said both implanting steps are performed prior to patterning.

12. The method of claim 10 wherein said selectively forming a compressive metal comprises forming a hard mask over said PFET, removing exposed portions of the Si-containing second gate electrode layer in said NFET, and depositing said compressive metal in the area previously containing the Si-containing second gate electrode layer.

13. The method of claim 10 wherein said tensile metal comprises Ta.

14. The method of claim 10 wherein said compressive metal comprised Ta.

15. The method of claim 10 wherein said compressive metal is sputtered deposited at a low pressure and a high substrate bias.

16. The method of claim 10 wherein said tensile metal is sputtered deposited at a high pressure and at no substrate bias.