Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming

• US 7,314,798 B2
• Filed: 07/25/2005
• Issued: 01/01/2008
• Est. Priority Date: 07/25/2005
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chindalore, Gowrishankar L., Hong, Cheong M., Swift, Craig T.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Stark, Jarrett J
• Application Number:
  US11/188,583
• Publication Number:
  US 20070020831A1
• Time in Patent Office: 890 Days
• Field of Search: 438/197, 438/259, 438/589, 257/E21.679, 257/E27.103, 257/E21.422, 257/E21.646, 257/E29.304
• US Class Current: 438/259
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

Claims

1. A method of fabricating a storage device in an array of storage devices, comprising:

forming first and second trenches in a semiconductor substrate, wherein;

the first trench and the second trench spaced-apart from one another;

each of the first trench and the second trench extends from a surface of the semiconductor substrate; and

a portion of the semiconductor substrate lies between and immediately adjacent to a first wall of the first trench and a second wall of the second trench;

forming first and second source/drain regions underlying the first and second trenches respectively;

forming a charge storage stack, wherein the charge storage stack lines the first and second trenches and overlies a portion of the semiconductor substrate between the first and second trenches, and wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs); and

forming a first control gate overlying the first source/drain regions and the charge storage stack, wherein a set of the DSEs overlie the portion of the semiconductor substrate between the first and second trenches, and the set of DSEs lies between the first control gate and the portion of the semiconductor substrate; and

forming a first diffusion region between the first and second trenches, wherein;

the first diffusion region lies within the portion of the semiconductor substrate and at the surface of the semiconductor substrate; and

the first diffusion region is spaced apart from the first wall, the second wall, or both the first and second walls.

2. The method of claim 1, wherein forming a first diffusion region comprises forming the first diffusion region after forming the first and second source/drain regions and after forming the first control gate.

3. The method of claim 2, wherein forming the first control gate includes forming a first control gate, wherein from a top view, each of the first trench and the first control gate has a width and a length that is greater than its corresponding width, and wherein the length of the first control gate is parallel to the length of the first trench.

4. The method of claim 3, further comprising isolating the first diffusion region by implanting second diffusion regions into the portion of the semiconductor substrate, wherein:

the first diffusion region lies between the second diffusion regions; and

the first diffusion region has a conductivity type opposite that of the second diffusion regions.

5. The method of claim 2, further comprising forming a second diffusion region between the first and second trenches after forming the first control gate, wherein:

the second diffusion region lies within the portion of the semiconductor substrate and at the surface of the semiconductor substrate;

the second diffusion region is spaced apart from the first wall, the second wall, or both the first and second walls;

the second diffusion region is spaced apart from the first diffusion region; and

the first and second diffusion regions lie along opposite sides of the first control gate.

6. The method of claim 5, wherein forming the first control gate comprises forming a first control gate, wherein from a top view, each of the first and second trenches and the first control gate has a width and a length that is greater than its corresponding width, and wherein the length of the first control gate is perpendicular to the lengths of the first and second trenches wherein the first control gate traverses the first and second trenches.

7. The method of claim 1, wherein forming the first and second trenches includes forming a dielectric liner on the substrate and a hard mask on the dielectric liner, patterning the dielectric liner and the hard mask;

and etching portion of the substrate exposed by the patterned liner and hard mask.

8. A method of fabricating a storage device in an array of storage devices, comprising:

forming first and second trenches in a semiconductor substrate;

forming first and second source/drain regions underlying the first and second trenches respectively;

lining the first and second trenches with a charge storage stack, wherein the charge storage stack includes a layer of discontinuous storage elements (DSEs);

forming a first control gate overlying the first source/drain regions; and

forming a first diffusion region occupying an upper portion of the substrate between the first and second trenches wherein forming the first diffusion region is performed after lining the first and second trenches with the charge storage stack.

9. The method of claim 8, wherein the first diffusion region contacts metalization only outside of the array.

10. The method of claim 8, wherein forming the first control gate includes forming a first control gate, wherein from a top view, each of the first trench and the first control gate has a width and a length that is greater than its corresponding width, and wherein the length of the first control gate is parallel to the length of the first trench.

11. The method of claim 10, further comprising isolating the first diffusion region by implanting second diffusion regions into the portion of the semiconductor substrate, wherein:

the first diffusion region lies between the second diffusion regions; and

the first diffusion region has a conductivity type opposite that of the second diffusion regions.

12. The method of claim 8, further comprising forming a second diffusion region between the first and second trenches after forming the first control gate, wherein:

the second diffusion region lies within the portion of the semiconductor substrate and adjacent to the surface of the semiconductor substrate;

the second diffusion region is spaced apart from the first diffusion region;

the first and second diffusion regions lie along opposite sides of the first control gate; and

forming the first diffusion region and forming the second diffusion region are performed after forming the first control gate.

13. The method of claim 12, wherein forming the first control gate comprises forming a first control gate, wherein from a top view, each of the first and second trenches and the first control gate has a width and a length that is greater than its corresponding width, and wherein the length of the first control gate is perpendicular to the lengths of the first and second trenches wherein the first control gate traverses the first and second trenches.

14. The method of claim 8, wherein forming the first and second trenches includes forming a dielectric liner on the substrate and a hard mask on the dielectric liner, patterning the dielectric liner and the hard mask;

and etching portion of the substrate exposed by the patterned liner and hard mask.

15. The method of claim 12, wherein:

forming the first and second trenches, such that the first trench has a first wall, and the second trench has a second wall;

lining the first and second trenches with a charge storage stack comprises forming the layer of DSEs along the first wall of the first trench, along the second wall of the second trench, and over a portion of the semiconductor substrate lying between the first wall and the second wall; and

the method further comprises forming a second control gate spaced apart from the first control gate; and

forming the first diffusion region comprises forming the first diffusion region in the semiconductor substrate between the first control gate and the second control gate, wherein forming the first diffusion region is formed after forming the first control gate and forming the second control gate.

16. The method of claim 15, wherein forming the first diffusion region comprises forming the first diffusion region spaced apart from the first wall, the second wall, or both the first and second walls.

17. The method of claim 16, further comprising forming isolation regions by implanting second diffusion regions in the portion of the semiconductor substrate, wherein:

the first diffusion region lies between the second diffusion regions; and

the first diffusion region has a conductivity type opposite that of the second diffusion regions.

19. The method of claim 15, wherein forming the first control gate comprises forming the first control gate, wherein from a top view, each of the first trench and the first control gate has a width and a length that is greater than its corresponding width, and wherein the length of the first control gate is perpendicular to the length of the first trench.

20. The method of claim 19, further comprising:

forming a second trench within the semiconductor substrate, wherein the second trench is spaced apart from the first trench, aid the surface at the top of the first wall extends to the second trench; and

forming a second source/drain region underlying the second trench, wherein the second source/drain region has the first conductivity type.

18. A method of fabricating a storage device, comprising:

forming a first trench in a semiconductor substrate, wherein;

the first trench has a first wall, wherein the first wall has a top and a bottom; and

the semiconductor substrate has a surface at the top of the first wall;

forming a first source/drain region underlying the first trench, wherein the first source/drain region has a first conductivity type;

forming a gate dielectric layer along the first wall of the trench and the surface of the semiconductor substrate;

forming a layer of discontinuous storage elements (DSEs) over the gate dielectric layer; and

forming a first control gate overlying the first trench, wherein the first control gate overlies a set of DSEs, wherein the set of DSEs overlies the portion of the semiconductor substrate, wherein after forming the first control gate, substantially all of the portion of the semiconductor substrate that is immediately adjacent to the surface and directly below the first control gate has a second conductivity type that is opposite the first conductivity type.