Structure and method for manufacturing strained FINFET

• US 7,314,802 B2
• Filed: 01/31/2007
• Issued: 01/01/2008
• Est. Priority Date: 02/15/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Zhu, Huilong
• Primary Examiner(s): Hu; Shouxiang
• Application Number:
  US11/669,598
• Publication Number:
  US 20070122984A1
• Time in Patent Office: 335 Days
• Field of Search: 438/283, 438/157, 438/176, 257/413, 257/353, 257/E21.442, 257/E21.623, 257/E21.637
• US Class Current: 438/283
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively etched to form a gate gap that makes the gate thin enough to be fully silicidated. After silicidation, the gate-gap is filled with a stress nitride film to create stress in the channel and enhance the performance of the FINFET.

Claims

1. A method for fabricating a strained fin field effect transistor (FINFET) that uses stress material to replace a part of the gate to apply stress to the channel of the FINFET, comprising:

fabricating the FINFET with a source, a drain and a stacked gate comprised of two different types of semiconductor materials that have different etching characteristics;

selectively etching one of the two different types of semiconductor materials of the stacked gate to form a gate gap;

refilling the gate gap with a stress film to create stress in the FINFET channel, to enhance electron and hole mobility and to improve the performance of the FINFET.

2. The method of claim 1, including fabricating the stacked gate as a poly-SiGe/poly-Si stacked gate, and selectively etching the poly-SiGe part of the gate to form the gate gap.

3. The method of claim 1, including refilling the gate gap with a stress nitride film to create stress in the FINFET channel.

4. The method of claim 1, including refilling the gate gap with a compressive stress nitride film to create stress in a pFINFET channel.

5. The method of claim 1, including refilling the gate gap with a tensile stress nitride film to create stress in an nFINFET channel.

6. The method of claim 1, including covering the FINFET with a further stress nitride film to further stress the channel.

7. The method of claim 1, including covering an nFINFET with a further tensile stress nitride film to further stress the channel of the nFINFET.

8. The method of claim 1, including covering a pFINFET with a further compressive stress nitride film to further stress the channel of the pFINFET.

9. A method for fabricating a strained fin field effect transistor (FINFET) that uses stress material to replace a part of the gate to apply stress to the channel of the FINFET, comprising:

starting with a Si fin having a sidewall protection layer on sidewalls of the Si fin, depositing a layer of poly-Si and then a layer of poly-SiGe on the Si fin;

patterning photoresist (PR) for a gate reactive ion etch (RIE);

RIE poly-SiGe and RIE the poly-Si to form a gate;

Etching the poly-SiGe selective to poly-Si, wherein the SiGe part of the gate is etched away to form a gap in the gate;

forming silicide contacts; and

depositing stress film to fill the gap in the gate.

10. The method of claim 9, wherein following the RIE steps:

implanting dopant for extension formation;

depositing nitride and RIE the nitride to form nitride spacers on the gate sidewalls; and

source and drain (S/D) dopant implantation and annealing.

11. The method of claim 9, wherein following the RIE steps:

thermally re-oxidizing the gate sidewalls to form a thin oxide to protect the gate sidewalls and/or to act as a spacer for extension implantation; and

angled dopant implantation for extension formation.

12. The method of claim 9, wherein following the step of depositing stress film, isotropically etching back the stress film to remove the stress film in source and drain areas.

13. The method of claim 9, including forming silicide contacts by wet etching thin oxide in source and drain areas, depositing thin Ni and annealing to form NiSi.

14. The method of claim 9, including depositing compressive stress nitride film for a pFINFET.

15. The method of claim 9, including depositing tensile stress nitride film for an nFINFET.

16. The method of claim 9, including covering the FINFET with another stress nitride film to further stress the channel.

17. The method of claim 9, including covering an nFINFET with another tensile stress nitride film to further stress the channel.

18. The method of claim 9, including covering a pFINFET with another compressive stress nitride film to further stress the channel.