Adjusting frequency device of built-in oscillator for USB interface and method thereof

• US 7,315,216 B2
• Filed: 04/21/2006
• Issued: 01/01/2008
• Est. Priority Date: 03/01/2006
• Status: Active Grant

• Current Assignee: Holtek Semiconductor Incorporated
• Original Assignee: Holtek Semiconductor Incorporated
• Inventors: Liu, Hsiang-Sheng, Yang, Chih-Wei, Lee, Chien-Hsun, Shiau, Juh-Gua
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US11/408,040
• Publication Number:
  US 20070216487A1
• Time in Patent Office: 620 Days
• Field of Search: 331/1.A, 331/14, 331 17- 18, 331/25, 327156-159, 332/127, 360/51, 375/376, 455/260, 710/61, 713400-401
• US Class Current: 331/25
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

An adjusting frequency device of built-in oscillator for USB interface and a method thereof are described. It is Auto detect the error of bit-rate between the USB host and the USB device, and produce tiny counting time for clocking the clock error between the USB host and the USB device by a delay lock loop. The clock error after quantification, digitization and operation outputting a quantitative code, then the oscillator adjusts the oscillation frequency according to the quantitative code. Whereby adjusting the oscillation frequency of the USB device and the frequency of the USB host to less than 1% clock error for ensuring the accuracy of data transmission.

Claims

1. An adjusting frequency device of built-in oscillator for USB interface, comprising:

a delay lock loop (DLL), which provides a reference signal of a time sector;

an error compare module, which receives a USB reference signal and a feedback signal, and outputs a quantitative value according to the reference signal of the time sector;

a computation module, which computes the quantitative value, and converts the obtained quantitative value into a quantitative code;

an oscillator, which adjusts the oscillation frequency of the oscillator based on the quantitative code;

a first frequency divider, which performs frequency division on the oscillation frequency of the oscillator, then outputs the feedback signal to the error compare module; and

a second frequency divider, which performs frequency division on the oscillation frequency of the oscillator, then provides a frequency-adjusted output signal.

2. The adjusting frequency device according to claim 1, wherein the adjusting frequency device furthermore comprises a controller, which is electrically connected to the error compare module, the computation module and the first frequency divider, in order to control the actions of the error compare module, the computation module and the first frequency divider.

3. The adjusting frequency device according to claim 1, wherein the error compare module quantifies the error time between the reference signal of the USB and the feedback signal based on the reference signal of the time sector, in order to output the quantitative value.

4. The adjusting frequency device according to claim 3, wherein the error compare module quantifies the error time between the reference signal of the USB and the feedback signal by using the time sector points generated from the reference signal of the time sector, in order to output the quantitative value.

5. The adjusting frequency device according to claim 1, wherein the quantitative value is obtained in a way that the computation module performs addition/subtraction operations, then converts to the said quantitative value.

6. The adjusting frequency device according to claim 1, wherein the computation module converts the computed quantitative value into the quantitative code receivable for the oscillator by means of a mapping design table.

7. The adjusting frequency device according to claim 6, wherein the mapping design table designs the adjustment capacity range of the oscillation frequency in the oscillator by means of setting the number of bits in the quantitative code.

8. An adjusting frequency device of built-in oscillator for USB interface, comprising:

a delay lock loop (DLL), which provides a reference signal of a time sector;

an error compare module, which compares a USB reference signal and a feedback signal, then outputs a compared error signal;

a multiplexing quantifier, which quantifies the error signal according to the reference signal of the time sector, and outputs a quantitative value and an operation reference signal;

a conversion unit, which receives and digitalizes the quantitative value;

a computation module, which receives the operation reference signal and the digitalized quantitative value, and outputs a second quantitative code after being operated with a first quantitative code;

an oscillator, which adjusts the oscillation frequency of the oscillator according to the second quantitative code;

a first frequency divider, which performs frequency division on the oscillation frequency of the oscillator, then outputs the feedback signal to the error compare module; and

a second frequency divider, which performs frequency division on the oscillation frequency of the oscillator, then provides a frequency-adjusted output signal.

9. The adjusting frequency device according to claim 8, wherein the multiplexing quantifier quantifies the error signal according to reference signal of the time sector, and outputs the quantitative value.

10. The adjusting frequency device according to claim 9, wherein the multiplexing quantifier quantifies the error signal by using the time sector points generated from the reference signal of the time sector, and outputs the quantitative value.

11. The adjusting frequency device according to claim 8, wherein the multiplexing quantifier designs the required quantitative value range according to difference of the reference signal frequencies of the time sector.

12. The adjusting frequency device according to claim 8, wherein the first quantitative code is the signal which the second quantitative code feeds back to the computation module.

13. The adjusting frequency device according to claim 8, wherein the second quantitative code is obtained in a way that the computation module, according to the operation reference signal, performs addition/subtraction operations on the digitalized quantitative value and the first quantitative code.

14. The adjusting frequency device according to claim 8, wherein the computation module converts the computed quantitative value into the second quantitative code receivable for the oscillator by means of a mapping design table.

15. The adjusting frequency device according to claim 14, wherein the mapping design table designs the adjustment capacity range of the oscillation frequency in the oscillator by means of setting the number of bits in the second quantitative code.

16. An adjusting frequency method of built-in oscillator for USB interface, wherein steps thereof comprise:

accessing a USB reference signal and a feedback signal;

detecting the error time between the USB reference signal and the feedback signal;

using a reference signal of a time sector to quantify the error time between the USB reference signal and the feedback signal;

computing the quantified error times, and converting the results into a quantitative code; and

adjusting the oscillation frequency of an oscillator according to the quantitative code.

17. The adjusting frequency method according to claim 16, wherein the feedback signal is the signal that output after the oscillation frequency of the oscillator being frequency divided by a frequency divider.

18. The adjusting frequency method according to claim 16, further comprises:

outputting an adjusted clock signal after the oscillation frequency of the oscillator being frequency divided by a frequency divider.

19. The adjusting frequency method according to claim 16, wherein an error compare module is used to access the USB reference signal and the feedback signal, in order to detect the error time between the USB reference signal and the feedback signal.

20. The adjusting frequency method according to claim 16, wherein the reference signal of the time sector provides time sector points to quantify the error time between the USB reference signal and the feedback signal.

21. The adjusting frequency method according to claim 20, wherein the reference signal of the time sector is provided by a delay lock loop (DLL).

22. The adjusting frequency method according to claim 21, wherein a multiplexing quantifier is used to design in accordance with the reference signal of the time sector with various frequencies provided by the delay lock loop, in order to design the number of time sector points between the USB reference signal and the feedback signal.

23. The adjusting frequency method according to claim 22, wherein a multiplexing quantifier is used to quantify the error time between the USB reference signal and the feedback signal.

24. The adjusting frequency method according to claim 16, wherein the quantified error time is generated by the addition/subtraction operations performed by a computation module.

25. The adjusting frequency method according to claim 16, wherein the quantified error time, after operations, is converted into the quantitative code by means of a mapping design table.

26. The adjusting frequency method according to claim 25 wherein the mapping design table designs the adjustment capacity range of the oscillation frequency in the oscillator by means of setting the number of bits in the quantitative code.