Method and apparatus to center the frequency of a voltage-controlled oscillator

• US 7,315,218 B1
• Filed: 12/28/2005
• Issued: 01/01/2008
• Est. Priority Date: 12/28/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Fernandez, Francisco
• Primary Examiner(s): Lee; Benny
• Assistant Examiner(s): JOHNSON, RYAN
• Application Number:
  US11/321,386
• Time in Patent Office: 734 Days
• Field of Search: 331/10, 331/11, 331/16, 331/18, 331/25, 331/34, 331/36.C, 331/1.A, 331/44, 331/175, 331/177.V, 331/177.R, 327/156, 327/157
• US Class Current: 331/44
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

A circuit and method are provided for calibrating an analog oscillator in the digital domain. The circuit and method disclosed herein centers an oscillation frequency of an analog oscillator by producing a binary signal to which the analog oscillator is responsive. Changes in the binary digital signal cause the oscillation frequency of the analog oscillator to shift in a desired direction to calibrate the analog oscillator. At the completion of the calibration process, the control of the oscillation frequency of the analog oscillator is switched to the analog domain so that the analog oscillator is responsive to an analog control voltage to shift the oscillation frequency.

Claims

1. A Phase Locked Loop (PLL) circuit comprising,

a Voltage Controlled Oscillator (VCO) responsive to a digital control signal received on a first input node to set a frequency of the VCO to correspond to a mid-range voltage of an analog control signal received on a second input node;

and

a frequency calibration circuit responsive to a plurality of input signals received on a plurality of input nodes to drive an output node with the digital control signal to set the frequency of the VCO, the frequency calibration circuit comprising;

a frequency detector to detect a frequency difference between a feedback signal and a reference signal and drive an output node with an output signal representative of the detected frequency difference;

a counter responsive to the output signal of the frequency detector to generate and output the digital control signal;

a controller configured to control a calibration process of the VCO; and

a clock generator configured to generate a first clock to clock the controller and to generate a second clock to clock the frequency detector;

wherein a change in the digital control signal represents a frequency shift to set the frequency of the VCO.

2. The PLL of claim 1 further comprising,

a frequency divider to divide a frequency of an output signal of the VCO and drive an output node with a feedback signal representative of the divided frequency of the output signal;

a phase-frequency detector to detect any of a frequency difference between the feedback signal and a reference signal or a phase difference between the feedback signal and the reference signal, and generate an output signal at either a first output node or a second output node related to any of the frequency difference or the phase difference between the feedback signal and the reference signal; and

a charge-pump having a first input node to receive the output signal driven by the phase-frequency detector on the first output node and a second input node to receive the output signal drive by the phase-frequency detector on the second output node and in response to the output signal from the first output node sources current and in response to the output signal from the second output node sinks current to generate an output charge current proportional to the phase difference detected by the phase-frequency detector.

3. The PLL of claim 2 further comprising, a loop filter configured to convert the charge-pump current into the analog control voltage signal.

4. The PPL of claim 1 further comprising, a switch configured to switch the VCO between a calibration mode and an operational mode.

5. The PLL of claim 1, wherein a value the digital control signal increases when a frequency of the feedback signal is greater than a frequency of the reference signal.

6. The PLL of claim 1, wherein a value of the digital control signal decreases when a frequency of the feedback signal is less then a frequency of the reference signal.

7. The PLL of claim 1, wherein a value of the digital control signal increases when a frequency of the reference signal is greater than a frequency of the feedback signal.

8. The PLL of claim 1, wherein the value of the digital control signal decreases when a frequency of the reference signal is less than a frequency of the feedback signal.

9. A Phase Locked Loop (PLL) circuit comprising,

a Voltage Controlled Oscillator (VCO) responsive to a digital control signal received on a first input node to set a frequency of the VCO to correspond to a mid-range voltage of an analog control signal received on a second input node;

and

a frequency calibration circuit responsive to a plurality of input signals received on a plurality of input nodes to drive an output node with the digital control signal to set the frequency of the VCO, the frequency calibration circuit comprising;

a frequency detector to detect a frequency difference between a feedback signal and a reference signal and drive an output node with an output signal representative of the detected frequency difference;

a counter responsive to the output signal of the frequency detector to generate and output the digital control signal; and

a controller configured to control a calibration process of the VCO, the controller, comprising a count detector configured to disable the counter when the value of the digital control signal reaches a predefined value;

wherein a change in the digital control signal represents a frequency shift to set the frequency of the VCO.

10. The PLL of claim 9, wherein the controller further comprises, a reversal detector configured to detect a reversal of polarity of the frequency difference between the feedback and the reference signals.

11. The PLL of claim 10 wherein the controller further comprises, a bypass circuit configured to bypass an output of the reversal detector.

12. The PLL of claim 11 wherein the controller further comprises, a calibration complete circuit configured to detect when the calibration of the VCO completes.

13. A method for calibrating a voltage controlled oscillator (VCO), the method comprising the steps of:

detecting a frequency difference between a frequency of a feedback signal of the VCO and a frequency of a reference signal;

changing a count of a counter based on the frequency difference;

halting calibration of the VCO when any of the following occur;

the count equals a predetermined value;

when the change to the count causes a reversal in a count direction of the counter, or when the change to the count would cause a reversal in a count direction of the counter; and

disabling the counter when the value of the digital control signal reaches a predefined value.

14. The method of claim 13 further comprising the step of, changing a capacitance value of the VCO based on the count of the counter.

15. The method of claim 13, wherein the step of detecting detects a polarity of the frequency difference between the frequency of the feedback signal of the VCO and the frequency of the reference signal.

16. The method of claim 13 further comprising the step of, bypassing the step of halting.

17. A calibration circuit for calibrating an analog oscillator circuit in a digital domain, the calibration circuit comprising:

an input circuit to initiate calibration of the analog oscillator circuit in the digital domain and output a digital output signal representing a result of a comparison between a frequency of a reference signal received on a first input node and a frequency of a feedback signal from the analog oscillator circuit received on a second input node;

an output circuit responsive to the digital output signal to change a digital value of a calibration signal generated by the output circuit, the change in the value of the calibration signal changing an electrical characteristic of the analog oscillator circuit from the digital domain to calibrate the analog circuit;

a controller configured to halt calibration when either the value of the calibration signal reaches a predetermined value, a change in direction of a binary count occurs, or a change in direction of a binary count would occur, wherein a value of the binary count is represented by the calibration signal; and

a clock generator configured to generate a first clock to clock the controller and to generate a second clock to clock the input circuit.