Non-volatile memory device

• US 7,315,472 B2
• Filed: 05/25/2006
• Issued: 01/01/2008
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Hee Youl
• Primary Examiner(s): Hur; Jung (John) H.
• Application Number:
  US11/420,367
• Publication Number:
  US 20070047366A1
• Time in Patent Office: 586 Days
• Field of Search: 365/185.11, 365/185.17, 365/230.03, 365/185.05, 365/185.13, 365/185.06
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits

Abstract

A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.

Claims

1. A non-volatile memory device comprising:

a plurality of memory blocks each of the memory blocks including memory cells, the memory cells being connected in series to bit lines, respectively, wherein each of the plurality of memory blocks comprises;

a first sub-memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines associated with the first group of memory cells, respectively, and second select transistors connected to a common source line; and

a second sub-memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines associated with the second group of memory cells, respectively, and fourth select transistors connected to the common source line;

wherein memory cells within each memory block are connected to N word lines, the first sub-memory block is connected to 1/2N word lines of the N word lines, and the second sub-memory block is connected to the remaining 1/2N word lines of the N word lines, and

wherein 1/2N word lines of the first sub-memory block and first and second select lines of the first and second select transistors are connected to 1/2N global word lines and first and second global select lines, respectively, through a first sub block select switch unit, and

1/2N word lines of the second sub-memory block and third and fourth select lines of the third and fourth select transistors are connected to the remaining 1/2N global word lines and the first and second global select lines, respectively, through a second sub block select switch unit.

2. The non-volatile memory device as claimed in claim 1, wherein during a program operation, if one of the first and second sub-memory blocks performs the program operation, the other of the first and second sub-memory blocks does not perform the program operation.

3. The non-volatile memory device as claimed in claim 1, wherein during a read operation, if one of the first and second sub-memory blocks performs the read operation, the other of the first and second sub-memory blocks does not perform the read operation.

4. The non-volatile memory device as claimed in claim 1, wherein during an erase operation, if one of the first and second sub-memory blocks performs the erase operation, the other of the first and second sub-memory blocks does not perform the erase operation.

5. The non-volatile memory device as claimed in claim 1, wherein during an erase operation, both the first and second sub-memory blocks perform the erase operation.

6. The non-volatile memory device as claimed in claim 1, wherein during a repair operation, one of the first and second sub-memory blocks is repaired.

7. The non-volatile memory device as claimed in claim 1, wherein if one of the first and second sub-memory blocks is selected by first and second block select signals, 1/2N word lines within a non-selected sub-memory block exist as a floating state and third and fourth select lines of the third and fourth select transistors also exist as a floating state, during a program operation.

8. The non-volatile memory device as claimed in claim 1, wherein if one of the first and second sub-memory blocks is selected by first and second block select signals, 1/2N word lines within a non-selected sub-memory block exist as a floating state and third and fourth select lines of the third and fourth select transistors are applied with 0V, during a read operation.

9. The non-volatile memory device as claimed in claim 1, wherein during program, read and, erase operations, only one of the first and second sub block select switch units is driven, and the other of the first and second sub block select switch units is not driven, whereby only one of the first and second sub-memory blocks is driven and the other of the first and second sub-memory blocks is not driven.

10. The non-volatile memory device as claimed in claim 1, wherein during an erase operation, both the first and second sub block select switch units are driven whereby both the first and second sub-memory blocks are driven.

11. A non-volatile memory device comprising:

a plurality of memory blocks each of the memory blocks including memory cells, the memory cells being connected in series to bit lines, respectively, wherein each of the plurality of memory blocks comprises;

a first sub-memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines associated with the first group of memory cells, respectively, and second select transistors connected to a common source line; and

a second sub-memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines associated with the second group of memory cells, respectively, and fourth select transistors connected to the common source line;

wherein memory cells within each memory block are connected to N word lines, the first sub-memory block is connected to 1/2N word lines of the N word lines, and the second sub-memory block is connected to the remaining 1/2N word lines of the N word lines, and,

wherein 1/2N word lines of the first sub-memory block and first and second select lines of the first and second select transistors are connected to 1/2N global word lines and first and second global select lines, respectively, through a first sub block select switch unit, and

1/2N word lines of the second sub-memory block and third and fourth select lines of the third and fourth select transistors are connected to the remaining 1/2N global word lines and third and fourth global select lines, respectively, through a second sub block select switch unit.

12. The non-volatile memory device as claimed in claim 11, wherein if one of the first and second sub-memory blocks is selected by first and second block select signals, 1/2N word lines within a non-selected sub-memory block exist as a floating state and third and fourth select lines of the third and forth select transistors also exist as a floating state, during a program operation.

13. The non-volatile memory device as claimed in claim 11, wherein if one of the first and second sub-memory blocks is selected by first and second block select signals, 1/2N word lines within a non-selected sub-memory block exist as a floating state and third and fourth select lines of the third and fourth select transistors are applied with 0V, during a read operation.

14. The non-volatile memory device as claimed in claim 11, wherein during program, read and, erase operations, only one of the first and second sub block select switch units is driven, and the other of the first and second sub block select switch units is not driven, whereby only one of the first and second sub-memory blocks is driven and the other of the first and second sub-memory blocks is not driven.

15. The non-volatile memory device as claimed in claim 11, wherein during an erase operation, both the first and second sub block select switch units are driven whereby both the first and second sub-memory blocks are driven.

16. The non-volatile memory device as claimed in claim 11, wherein during a program operation, if one of the first and second sub-memory blocks performs the program operation, the other of the first and second sub-memory blocks does not perform the program operation.

17. The non-volatile memory device as claimed in claim 11, wherein during a read operation, if one of the first and second sub-memory blocks performs the read operation, the other of the first and second sub-memory blocks does not perform the read operation.

18. The non-volatile memory device as claimed in claim 11, wherein during an erase operation, if one of the first and second sub-memory blocks performs the erase operation, the other of the first and second sub-memory blocks does not perform the erase operation.

19. The non-volatile memory device as claimed in claim 11, wherein during an erase operation, both the first and second sub-memory blocks perform the erase operation.

20. The non-volatile memory device as claimed in claim 11, wherein during a repair operation, one of the first and second sub-memory blocks is repaired.