Shared CODEC in multiprocessor systems

• US 7,315,556 B1
• Filed: 07/31/2000
• Issued: 01/01/2008
• Est. Priority Date: 07/31/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Ma, Zhigang, Petryna, Brian J., Yee, Oceager P.
• Primary Examiner(s): Chin; Wellington
• Assistant Examiner(s): Mais; Mark A.
• Application Number:
  US09/629,707
• Time in Patent Office: 2,710 Days
• Field of Search: 370/294, 370/321, 370/347, 370/442, 370/465, 370/470, 370/537, 370/535, 370/538, 370/539, 370/540, 370/541, 370/542, 370/543, 370/544, 370/545
• US Class Current: 370/540
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

A single coder/decoder shared among several multiprocessors in a digital signal processing system through time-division multiplexing between multiple processors to enhance signal processing capabilities by assigning different digital-to-analog channels to different processors for digital-to-analog conversion, while allowing all processors to operate on the same analog-to-digital data for analog-to-digital conversion, thereby resulting in chip area reduction and power consumption saving.

Claims

1. In a multiprocessor digital signal processing system, comprising:

a plurality of processors;

a single coder/decoder to selectively output an encoded signal to said plurality of processors through a time division multiplexed channel connecting said single coder/decoder to said plurality of processors;

a processor to selectively input to said coder/decoder one of a plurality of analog signals;

means for individually selecting input digital signals and analog signals for digital/analog conversion and analog/digital conversion, respectively; and

means for assigning which of said plurality of processors is coupled to said single digital/analog conversion channel.

2. The digital signal processing system according to claim 1, further comprising:

a plurality of registers to buffer digital signal data from said single coder/decoder to each of said first plurality of processors.

3. The digital signal processing system according to claim 2, further comprising:

means for individually selecting time slots for digital signals from each of said first plurality of processors to access said digital signal input of said coder/decoder.

4. A digital signal processing system comprising:

a single coder/decoder to communicate with a single digital/analog conversion channel, and to communicate with a single analog/digital conversion channel;

a processor to selectively input one of a plurality of digital signals and to selectively input one of a plurality of analog signals to said coder/decoder;

a first source of an analog input signal coupled to said analog signal input of said single coder/decoder;

a second source of digital input signals coupled to said digital signal input of said single coder/decoder;

a first plurality of processors multiplexed to said single coder/decoder; and

means for time division multiplexing said first plurality of processors to said single coder/decoder.

5. A digital signal processing system comprising:

a single coder/decoder to communicate with a single digital/analog conversion channel, and to communicate with a single analog/digital conversion channel;

a processor to selectively input one of a plurality of digital signals and to selectively input one of a plurality of analog signals to said coder/decoder;

a first source of an analog input signal coupled to said analog signal input of said single coder/decoder;

a second source of digital input signals coupled to said digital signal input of said single coder/decoder;

a first plurality of processors multiplexed to said single coder/decoder;

means for time division multiplexing said first plurality of processors to said single coder/decoder; and

a second plurality of processors coupled to a digital output of said single coder/decoder for operating on said single analog-to-digital converted signal.

6. A digital signal processing system, comprising:

a single coder/decoder to communicate with a single digital/analog conversion channel, and to communicate with a single analog/digital conversion channel;

a processor to selectively input one of a plurality of digital signals and to selectively input one of a plurality of analog signals to said coder/decoder;

a first source of an analog input signal coupled to said analog signal input of said single coder/decoder;

a second source of digital input signals coupled to said digital signal input of said single coder/decoder;

a first plurality of processors multiplexed to said single coder/decoder;

means for time division multiplexing said first plurality of processors to said single coder/decoder;

a second plurality of processors coupled to a digital output of said single coder/decoder for operating on said single analog-to-digital converted signal; and

a register to buffer digital signal data for use by said digital signal input of said single coder/decoder.