Methods and arrangements for link power reduction

• US 7,315,595 B2
• Filed: 12/22/2003
• Issued: 01/01/2008
• Est. Priority Date: 12/22/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Carballo, Juan-Antonio
• Primary Examiner(s): Tran; Khanh C.
• Application Number:
  US10/743,614
• Publication Number:
  US 20050135523A1
• Time in Patent Office: 1,471 Days
• Field of Search: 375/354, 375/316, 375/147, 375/355, 375/149, 375/368
• US Class Current: 375/355
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Methods, and arrangements for extension of clock and data recovery (CDR) loop latency and deactivation of CDR circuits are disclosed. In particular, embodiments address situations in which a receiver, designed to handle spread spectrum clocking, may not always or continuously encounter spread spectrum signals. As a result, power consumption by the receivers may be reduced. Embodiments identify situations in which spread spectrum clocking is unnecessary and may adapt the CDR loop to operate with less power consumption by, e.g., reducing the operating frequency of CDR circuits. For instance, some embodiments employ a flywheel circuit, incorporated into many spread spectrum CDR loops to accelerate adjustments to a sampling clock, to determine when spread spectrum signals are not being encountered. A loop latency controller may then, advantageously, reduce power consumption by reducing frequencies of operation and voltages, and merging or simplifying stages.

Claims

1. A method for reducing power consumption by a clock and data recovery loop circuit, the method comprising:

monitoring adjustments made in a phase of a sampling clock by a phase controller, the sampling clock being generated to sample bit values from a data signal;

modifying the adjustments in the phase of the sampling clock to track a phase of the data signal;

monitoring the modifications of the adjustments in the phase of the sampling clock;

determining the existence of spread spectrum clocking based upon a pattern of the modifications; and

adapting a stage of the clock and data recovery loop circuit in response to determining the existence of spread spectrum clocking to operate with less power consumption.

2. The method of claim 1, wherein adapting the stage comprises selecting a clock signal to modify an operating frequency for the stage.

3. The method of claim 1, wherein adapting the stage comprises determining a voltage select signal to reduce an operating voltage for the stage.

4. The method of claim 1, wherein adapting the stage comprises merging the stage with a second stage of the clock and data recovery loop circuit.

5. The method of claim 4, wherein merging the stage comprises bypassing a latch coupled between an output of the stage and an input of the second stage.

6. The method of claim 1, wherein adapting the stage comprises deactivating the stage and activating a second simpler stage, wherein the second simpler stage performs a substantially similar function as the stage.