Methods and arrangements for link power reduction
First Claim
1. A method for reducing power consumption by a clock and data recovery loop circuit, the method comprising:
- monitoring adjustments made in a phase of a sampling clock by a phase controller, the sampling clock being generated to sample bit values from a data signal;
modifying the adjustments in the phase of the sampling clock to track a phase of the data signal;
monitoring the modifications of the adjustments in the phase of the sampling clock;
determining the existence of spread spectrum clocking based upon a pattern of the modifications; and
adapting a stage of the clock and data recovery loop circuit in response to determining the existence of spread spectrum clocking to operate with less power consumption.
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Abstract
Methods, and arrangements for extension of clock and data recovery (CDR) loop latency and deactivation of CDR circuits are disclosed. In particular, embodiments address situations in which a receiver, designed to handle spread spectrum clocking, may not always or continuously encounter spread spectrum signals. As a result, power consumption by the receivers may be reduced. Embodiments identify situations in which spread spectrum clocking is unnecessary and may adapt the CDR loop to operate with less power consumption by, e.g., reducing the operating frequency of CDR circuits. For instance, some embodiments employ a flywheel circuit, incorporated into many spread spectrum CDR loops to accelerate adjustments to a sampling clock, to determine when spread spectrum signals are not being encountered. A loop latency controller may then, advantageously, reduce power consumption by reducing frequencies of operation and voltages, and merging or simplifying stages.
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Citations
6 Claims
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1. A method for reducing power consumption by a clock and data recovery loop circuit, the method comprising:
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monitoring adjustments made in a phase of a sampling clock by a phase controller, the sampling clock being generated to sample bit values from a data signal; modifying the adjustments in the phase of the sampling clock to track a phase of the data signal; monitoring the modifications of the adjustments in the phase of the sampling clock; determining the existence of spread spectrum clocking based upon a pattern of the modifications; and adapting a stage of the clock and data recovery loop circuit in response to determining the existence of spread spectrum clocking to operate with less power consumption. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification