Data processing performance control

• US 7,315,796 B2
• Filed: 05/10/2006
• Issued: 01/01/2008
• Est. Priority Date: 01/13/2003
• Status: Expired due to Term

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Flynn, David Walter
• Primary Examiner(s): Barlow; John
• Assistant Examiner(s): VO, HIEN XUAN
• Application Number:
  US11/430,903
• Publication Number:
  US 20060217927A1
• Time in Patent Office: 601 Days
• Field of Search: 702/182, 713/300, 713/320, 713/322
• US Class Current: 702/182
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor 46 operating under program instruction control generates a desired performance level request. A mapping circuit then maps this to a control signal, such as a thermometer coded control signal, which is supplied to further circuits which require control so as to support the desired data processing performance level. These further circuits can include a clock generator 4 and a voltage controller 6.

Claims

1. Apparatus for processing data, said apparatus comprising:

a processor operable to perform data processing operations under control of program instructions, said processor being operable under program instruction control to generate a performance level request signal indicative of a desired data processing performance level of said processor; and

a mapping circuit operable to map said performance level request signal into a control signal supplied to one or more further circuits to control operation of said one or more further circuits so as to support said desired data processing performance level of said processor such that said program instructions controlling generation of said performance level request signal are independent of how said one or more further circuits are controlled to meet said desired data processing performance level.

2. Apparatus as claimed in claim 1, wherein said one or more further circuits include a clock generator operable to generate a clock signal with a selectable clock frequency, said clock signal being supplied to said processor to drive said processing operations such that data processing performance of said processor varies in dependence upon which clock frequency is selected.

3. Apparatus as claimed in claim 2, wherein, in response to an increase in desired data processing performance level, said clock generator increases clock signal frequency to an intermediate clock signal frequency when said voltage controller is generating a power signal with a voltage level sufficient to support said intermediate clock signal frequency.

4. Apparatus as claimed in claim 2, wherein said clock generator is operable to generate a clock signal with one or more permanently available clock signal frequencies and one or more selectively available clock signal frequencies.

5. Apparatus as claimed in claim 4, wherein a permanently enabled PLL circuit is operable to generate said one or more permanently available clock signal frequencies and a selectively enabled PLL circuit is operable to generate said one or more selectively available clock signal frequencies.

6. Apparatus as claimed in claim 1, wherein said one or more further circuits include a voltage controller operable to generate a power supply signal, said power supply signal being supplied to said processor at a selectable voltage level, different voltage levels allowing different switching speeds within said processor such that a maximum usable data processing performance varies in dependence upon which voltage level is selected.

7. Apparatus as claimed in claim 1, wherein said control signal is a thermometer coded value.

8. Apparatus as claimed in claim 7, having a plurality of processors and mapping circuits operable to generate respective thermometer coded values which are logically combined to produce a combined thermometer coded value to control at least one of said one or more further circuits.

9. Apparatus as claimed in claim 1, wherein said mapping circuit performs a many to one mapping between performance level request signal values and corresponding control signal values.

10. Apparatus as claimed in claim 9, wherein said control signals are quantised such that a control signal value supports a maximum desired performance level within a range of desired performance levels having corresponding performance level request signal values mapped to said control signal value.

11. Apparatus as claimed in claim 1, wherein performance level supported as controlled by control signal value increases monotonically with performance level request signal value.

12. Apparatus as claimed in claim 1, wherein at least one of said one or more further circuits operates in a different clock domain to said processor.

13. Apparatus as claimed in claim 1, wherein at least one of said one or more further circuits is configured with one or more configuration values specifying how said further circuit should respond to different control signal values.

14. Apparatus as claimed in claim 13, wherein said configuration values specify voltage levels corresponding to different control signal values.

15. Apparatus as claimed in claim 1, wherein while responding to a change in performance control signal corresponding to a change from a first desired data processing performance level to a second desired data processing performance level, said one or more further circuits are operable to support data processing at at least one intermediate data processing performance level and said processor temporarily operates at said at least one intermediate data processing performance level during said change.

16. Apparatus as claimed in claim 15, wherein a priority signal serves to trigger said further circuit to change to support a predetermined data processing performance level independently of said performance control signal.

17. Apparatus as claimed in claim 1, wherein at least while responding to a change in said performance control signal, said further circuit is operable to generate a current operation signal indicative of current operation of said further circuit.

18. Apparatus as claimed in claim 17, wherein said current operation signal is indicative of a maximum power supply voltage of that can currently be supported by said voltage controller.

19. Apparatus as claimed in claim 18, wherein, in response to an increase in desired data processing performance level, said clock generator increases clock signal frequency when said voltage controller generates a current operation signal indicative of a generation of said power signal with a voltage level sufficient to support an increased clock signal frequency.

20. Apparatus as claimed in claim 17, wherein said current operation signal is indicative of a clock frequency that is currently being generated by said clock generator.

21. A method of processing data, said method comprising the steps of:

performing data processing operations with a processor under control of program instructions, said processor being operable under program instruction control to generate a performance level request signal indicative of a desired data processing performance level of said processor; and

mapping with a mapping circuit said performance level request signal into a control signal supplied to one or more further circuits to control operation of said one or more further circuits so as to support said desired data processing performance level of said processor such that said program instructions controlling generation of said performance level request signal are independent of how said one or more further circuits are controlled to meet said desired data processing performance level.

22. A method as claimed in claim 21, wherein said one or more further circuits include a clock generator operable to generate a clock signal with a selectable clock frequency, said clock signal being supplied to said processor to drive said processing operations such that data processing performance of said processor varies in dependence upon which clock frequency is selected.

23. A method as claimed in claim 22, wherein, in response to an increase in desired data processing performance level, said clock generator increases clock signal frequency to an intermediate clock signal frequency when said voltage controller is generating a power signal with a voltage level sufficient to support said intermediate clock signal frequency.

24. A method as claimed in claim 22, wherein said clock generator is operable to generate a clock signal with one or more permanently available clock signal frequencies and one or more selectively available clock signal frequencies.

25. A method as claimed in claim 24, wherein a permanently enabled PLL circuit is operable to generate said one or more permanently available clock signal frequencies and a selectively enabled PLL circuit is operable to generate said one or more selectively available clock signal frequencies.

26. A computer program product containing program instructions for controlling a processor to operate in accordance with the method as claimed in claim 22.

27. A method as claimed in claim 21, wherein said one or more further circuits include a voltage controller operable to generate a power supply signal, said power supply signal being supplied to said processor at a selectable voltage level, different voltage levels allowing different switching speeds within said processor such that a maximum usable data processing performance varies in dependence upon which voltage level is selected.

28. A method as claimed in claim 21, wherein said control signal is a thermometer coded value.

29. A method as claimed in claim 28, wherein a plurality of processors and mapping circuits generate respective thermometer coded values which are logically combined to produce a combined thermometer coded value to control at least one of said one or more further circuits.

30. A method as claimed in claim 21, wherein said mapping is a many to one mapping between performance level request signal values and corresponding control signal values.

31. A method as claimed in claim 30, wherein said control signals are quantised such that a control signal value supports a maximum desired performance level within a range of desired performance levels having corresponding performance level request signal values mapped to said control signal value.

32. A method as claimed in claim 21, wherein performance level supported as controlled by control signal value increases monotonically with performance level request signal value.

33. A method as claimed in claim 21, wherein at least one of said one or more further circuits operates in a different clock domain to said processor.

34. A method as claimed in claim 21, wherein at least one of said one or more further circuits is configured with one or more configuration values specifying how said further circuit should respond to different control signal values.

35. A method as claimed in claim 34, wherein said configuration values specify voltage levels corresponding to different control signal values.

36. A method as claimed in claim 21, wherein while responding to a change in performance control signal corresponding to a change from a first desired data processing performance level to a second desired data processing performance level, said one or more further circuits are operable to support data processing at at least one intermediate data processing performance level and said processor temporarily operates at said at least one intermediate data processing performance level during said change.

37. A method as claimed in claim 36, wherein a priority signal serves to trigger said further circuit to change to support a predetermined data processing performance level independently of said performance control signal.

38. A method as claimed in claim 21, wherein at least while responding to a change in said performance control signal, said further circuit is operable to generate a current operation signal indicative of current operation of said further circuit.

39. A method as claimed in claim 38, wherein said current operation signal is indicative of a maximum power supply voltage of that can currently be supported by said voltage controller.

40. A method as claimed in claim 39, wherein, in response to an increase in desired data processing performance level, said clock generator increases clock signal frequency when said voltage controller generates a current operation signal indicative of a generation of said power signal with a voltage level sufficient to support an increased clock signal frequency.

41. A method as claimed in claim 38, wherein said current operation signal is indicative of a clock frequency that is currently being generated by said clock generator.