Scratch pad block

• US 7,315,916 B2
• Filed: 12/16/2004
• Issued: 01/01/2008
• Est. Priority Date: 12/16/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Bennett, Alan David, Gorobets, Sergey Anatolievich
• Primary Examiner(s): Bragdon; Reginald
• Assistant Examiner(s): DINH, NGOC V
• Application Number:
  US11/016,285
• Publication Number:
  US 20060161722A1
• Time in Patent Office: 1,111 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

In a memory array having a minimum unit of erase of a block, a scratch pad block is used to store data that is later written to another block. The data may be written to the scratch pad block with a low degree of parallelism and later written to another location with a high degree of parallelism so that it is stored with high density. Data may be temporarily stored in the scratch pad block until it can be more efficiently stored elsewhere. This may be when some other data is received. Unrelated data may be stored in the same page of a scratch pad block.

Claims

1. A method of storing addressable units of data in a non-volatile memory array having a minimum unit of erase of a block and a minimum unit of program of a page, a page containing one or more addressable units of data, a page containing less data than a block, comprising:

writing a plurality of addressable units of data in a first block with a first degree of parallelism;

subsequently copying the plurality of addressable units of data to a second block where they are written in a write operation having a second degree of parallelism that is higher than the first degree of parallelism; and

subsequently writing additional addressable units of data to the first block while the first block contains the plurality of addressable units of data.

2. The method of claim 1 wherein the first degree of parallelism is less than the parallelism of programming a full page of data and the second degree of parallelism is the degree of parallelism of programming a full page of data.

3. The method of claim 1 wherein the plurality of addressable units of data form a portion of a first file, the portion containing less than one page of data, subsequent copying of the plurality of addressable units of data is in parallel with programming of a portion of a second file, such that the portion of the first file and the portion of the second file form a page of data in the second block.

4. The method of claim 1 wherein the second block contains a plurality of multi-level cells, the plurality of addressable units of data form a first page in the first block and are copied to the second block in parallel with writing a second page of data to the second block such that the first page and the second page form upper and lower pages of programming of the plurality of multi-level cells.

5. The method of claim 1 wherein the plurality of addressable units of data are written to the second block in parallel with additional data to achieve the second degree of parallelism.

6. A method of writing addressable units of data to multi-level cells in a non-volatile memory array, the memory array having a unit of erase of a block, a multi-level cell having more than two possible programmed states corresponding to more than one bit of data, comprising:

receiving a first addressable unit of data and a second addressable unit of data from a host;

programming the first addressable unit of data to both a first block and to a plurality of multi-level cells of a second block;

programming the plurality of multi-level cells of the second block according to bits of the second unit of data while the first addressable unit of data is held in the first block without programming the second addressable unit of data to the first block; and

subsequently marking the first addressable unit of data in the first block as obsolete only after verifying that the plurality of multi-level cells of the second block are fully programmed to states that reflect bits of the second unit of data.

7. The method of claim 6 wherein programming the plurality of multi-level cells of the second block according to bits of a second addressable unit terminates at an intermediate stage where a cell has not reached a state that reflects a bit of the second unit of data but the cell has been modified from a state that reflects a bit of the first unit of data and subsequently recovering the bits of the first unit of data from the first block.

8. The method of claim 6 wherein the first addressable unit of data is programmed to the first block at a first time, the first and second addressable units of data are subsequently programmed to the second block at a second time when the second addressable unit of data is received.

9. The method of claim 6 further comprising erasing the first block when all data in the first block is marked as obsolete.

10. A method of storing logically non-sequential addressable units of data in a non-volatile memory array having minimum units of erase of a block and minimum units of programming of a page, comprising:

storing a first at least one addressable unit of data in a first page of a first block;

storing a second at least one addressable unit of data in parallel with the first at least one addressable unit of data in the first page of the first block, the second at least one addressable unit of data not logically sequential with the first at least one addressable unit of data;

subsequently copying the first at least one addressable unit of data to a second block and copying the second at least one addressable unit of data to a third block; and

subsequently storing a third at least one addressable unit of data in the first block while the first block holds the first at least one addressable unit of data and the second at least one addressable unit of data.

11. The method of claim 10 wherein the first at least one addressable unit of data comprises host data and the second at least one addressable unit of data comprises control data.

12. The method of claim 10 wherein the first at least one addressable unit of data comprises a plurality of logically sequential addressable units of host data of a first file and the second at least one addressable unit of data comprises a plurality of logically sequential addressable units of host data of a second file.

13. The method of claim 10 wherein the third at least one addressable unit of data is stored in a second page of the first block, the third at least one addressable unit of data being logically non-sequential with both the first and second at least one addressable units of data.

14. The method of claim 13 wherein the first at least one unit of data contains data from a first file, the second at least one unit of data contains data from a second file and the third at least one unit of data contains data from a third file.

15. A method of storing data in a non-volatile memory array having memory cells arranged in minimum units of erase of an erase block, groups of erase blocks linked to form metablocks, a metapage being the unit of programming of a metablock, comprising:

storing a first sector of data in a first metapage of a first metablock;

storing at least a second sector in at least a second metapage of the first metablock;

writing the first sector of data, the at least a second sector of data and a third sector of data together to a metapage of a second metablock when the third sector of data is received; and

subsequently storing a fourth sector of data in the first metablock without erasing the first sector of data and the at least a second sector of data from the first metablock.

16. The method of claim 15 wherein the first sector of data, the at least a second sector of data and the third sector of data combined form a full metapage of data.

17. The method of claim 15 wherein subsequent to writing the first sector of data, the at least a second sector of data and the third sector of data together to a metapage of the second metablock, the first metablock is not immediately marked as obsolete.

18. The method of claim 15 wherein the first sector of data is copied from the first metapage to the at least a second metapage.

19. The method of claim 15 wherein the at least a second sector consists of a second sector and an additional sector, the first and second sectors being stored in the second metapage of the first metablock, the first, second and additional sectors being stored in a third metapage of the first metablock.

20. The method of claim 15 wherein the first sector of data, the at least a second sector of data and the third sector of data form a metapage of the second metablock.

21. A method of storing data in a non-volatile memory array having memory cells arranged in minimum units of erase of an erase block, a page being the minimum unit of programming of an erase block, comprising:

storing a first sector of data in a first page of a first erase block;

storing at least one additional sector in at least one additional page of the first erase block;

writing the first sector of data, the at least one additional sector of data and a final sector of data together to a page of a second erase block when the final sector of data is received; and

subsequently storing a second sector of data in the first erase block without erasing the first sector of data and the at least one additional sector from the first erase block.

22. The method of claim 21 wherein the first sector of data, the at least one additional sector of data and the final sector of data together completely fill the page of the second erase block.