Compiling HLL into massively pipelined systems

• US 7,315,991 B1
• Filed: 02/23/2005
• Issued: 01/01/2008
• Est. Priority Date: 02/23/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Bennett, David W.
• Primary Examiner(s): Dinh; Paul
• Application Number:
  US11/064,401
• Time in Patent Office: 1,042 Days
• Field of Search: 716/1, 716 3- 5, 716 16- 18, 712/1, 703 13- 15, 717/146, 714/725
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level

Abstract

A method of creating a circuit from a high level programming language (HLL) program can include generating a netlist from the HLL program, wherein the netlist specifies the circuit design (1320, 1325). The circuit design can be run within a programmable logic device and a plurality of execution threads can be identified at runtime to determine scheduling information (1335, 1340).

Claims

1. A method of creating a circuit from a high level programming language (HLL) program, said method comprising:

translating the HLL program into an assembly language program written in an assembly language, wherein the assembly language program comprises instructions corresponding to hardware components and pseudo instructions;

generating a netlist from the assembly language program, wherein the netlist specifies the circuit;

running the circuit within a programmable logic device and identifying a plurality of execution threads for the circuit at runtime to determine scheduling information; and

instantiating at least one hardware component in the programmable logic device based upon a conditional branching construct of the assembly language program, such that signal flow through the at least one hardware component is determined according to selected ones of the plurality of execution threads.

2. The method of claim 1, wherein the circuit executes the execution threads in parallel.

3. The method of claim 1, wherein the circuit executes the execution threads in a pipelined fashion.

4. The method of claim 1, said running step further comprising:

associating each of the plurality of execution threads with a sequence number; and

scheduling the circuit according to the sequence numbers.

5. The method of claim 1, said generating step further comprising creating hardware components for instructions of the assembly language program.

6. The method of claim 5, said generating step further comprising creating one hardware component for each instruction of the assembly language program.

7. The method of claim 5, said generating step further comprising creating first-in-first-outs for operands of the instructions of the assembly language program, wherein the first-in-first-outs link the hardware components.

8. The method of claim 1, said translating step further comprising:

identifying constructs of the HLL program; and

mapping the constructs to instructions and pseudo-instructions of the assembly language.

9. The method of claim 1, further comprising:

instantiating at least one hardware component in the programmable logic device based upon a looping construct of the assembly language program, such that signal flow through the at least one hardware component is determined according to selected ones of the plurality of execution threads.

10. A method of creating a circuit from a high level programming language (HLL) program, said method comprising:

translating the HLL program into an assembly language program written in an assembly language, wherein the assembly language program comprises instructions corresponding to hardware components and pseudo instructions;

generating a netlist from the intermediate format, wherein the netlist specifies the circuit;

running the circuit within a programmable logic device and identifying a plurality of execution threads for the circuit at runtime to determine scheduling information; and

instantiating at least one hardware component in the programmable logic device based upon a looping construct of the assembly language program, such that signal flow through the at least one hardware component is determined according to selected ones of the plurality of execution threads.

11. The method of claim 10, wherein running further comprises:

associating each of the plurality of execution threads with a sequence number; and

scheduling the circuit according to the sequence numbers.

12. The method of claim 10, further comprising:

creating hardware components for instructions of the assembly language program; and

creating first-in-first-outs for operands of the instructions of the assembly language program, wherein the first-in-first-outs link the hardware components.

13. The method of claim 10, said translating step further comprising:

identifying constructs of the HLL program; and

mapping the constructs to instructions and pseudo-instructions of the assembly language.

14. The method of claim 10, further comprising

instantiating at least one hardware component in the programmable logic device based upon a conditional branching construct of the assembly language program, such that signal flow through the at least one hardware component is determined according to selected ones of the plurality of execution threads.

15. A method of creating a circuit design from a high level programming language (HLL) program, said method comprising:

translating the HLL program into an assembly language program written in an assembly language, wherein instructions of the assembly language program correspond to hardware components;

generating a netlist from the assembly language program, wherein the netlist specifies the circuit design;

running the circuit design within a programmable logic device, said running step comprising;

identifying a plurality of execution threads for the circuit design at runtime;

associating each of the plurality of execution threads with a sequence number; and

scheduling the circuit design according to the sequence numbers; and

instantiating at least one hardware component in the programmable logic device based upon at least one of a looping construct or a conditional branching construct of the assembly language program, such that signal flow through the at least one hardware component is determined according to selected ones of the plurality of execution threads.