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Switching method in a multi-threaded processor

  • US 7,316,021 B2
  • Filed: 02/17/2004
  • Issued: 01/01/2008
  • Est. Priority Date: 05/11/1999
  • Status: Expired due to Term
First Claim
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1. A computing system comprising:

  • at least part of a memory hierarchy;

    a processor that stores plural execution contexts in a pipeline thereof, the processor performing a context switch between a first one and a second one of the execution contexts by freezing the first execution context in the pipeline and resuming execution using previously frozen state corresponding to the second execution context, the context switching performed without draining the first execution context from the pipeline;

    a context selectable storage distributed throughout the pipeline, the context selectable storage coupled into the pipeline to represent intermediate pipeline states for at least two concurrently executing execution contexts; and

    wherein at least some of the context-selectable storage distributed throughout the pipeline employs multi-bit flip-flops, wherein respective bits of each multi-bit flip-flop correspond to a selectable one of the execution contexts.

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