Fabricating method of a liquid crystal display device

• US 7,316,944 B2
• Filed: 09/28/2005
• Issued: 01/08/2008
• Est. Priority Date: 06/24/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Ahn, Byung Chul
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US11/236,831
• Publication Number:
  US 20060017054A1
• Time in Patent Office: 832 Days
• Field of Search: 438/149, 438/155, 438/158, 438/238, 257/E21.414
• US Class Current: 438/155
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A horizontal electric field applying type thin film transistor substrate of a LCD device having an increased aperture ratio as well as a simplified manufacturing process. The device includes a gate line having a double layered structure including a transparent first conductive layer and an opaque second conductive layer, a data line crossing the gate line to define a pixel area; a thin film transistor connected to the gate line and the data line; a common line having first and second conductive layers and substantially parallel to the gate line; a common electrode extended from the first conductive layer of the common line in the pixel area; and a pixel electrode connected to the thin film transistor to form a horizontal electric field with the common electrode in the pixel area.

Claims

1. A fabricating method of a liquid crystal display device, comprising:

forming a gate pattern having a double layered structure including a transparent first conductive layer and an opaque second conductive layer on a substrate, and a common pattern having a common line of the double layered structure and a common electrode formed of the first conductive layer using a first mask;

forming a gate insulating film on the gate pattern and the common pattern;

forming a semiconductor pattern on the gate insulating film, and a source/drain pattern having a data line, a source electrode and a drain electrode on the semiconductor pattern using a second mask;

forming a passivation film on the source/drain pattern, and a contact hole exposing the drain electrode using a third mask; and

forming a pixel electrode connected to the drain electrode through the contact hole using a fourth mask, wherein a horizontal field is formed with the common electrode,

wherein a line width of the first conductive layer of the common line is wider than a portion of the common line overlapped by the pixel electrode.

2. The method according to claim 1, further comprising:

forming a storage capacitor by an overlapping part of the pixel electrode and the common electrode, the gate insulating film and the passivation film therebetween.

3. The method according to claim 1, further comprising:

forming a storage capacitor by an overlapping part of the pixel electrode and the common line, the gate insulating film and the passivation film therebetween.

4. The method according to claim 1, further comprising:

forming a first storage capacitor overlapping a part of the pixel electrode and the common electrode with the gate insulating film and the passivation film therebetween; and

forming a second storage capacitor overlapping another part of the pixel electrode and a part of the common line, wherein the gate insulating film and the passivation film are therebetween.

5. The method according to claim 1, further comprising:

forming a light shielding layer overlapping the common electrode using the second conductive layer.

6. The method according to claim 5, wherein the light shielding layer is formed to have a line width so as to expose both side parts of the common electrode.

7. The method according to claim 1, further comprising:

forming a gate pad lower electrode having a double layered structure;

forming an another contact hole penetrating the gate insulating film and the passivation film; and

forming a gate pad upper electrode connected to the gate pad lower electrode through the another contact hole.

8. The method according to claim 7, wherein the contact hole is extended to penetrate to a second conductive layer of the gate pad lower electrode.

9. The method according to claim 1, further comprising:

forming a common pad lower electrode having a double layered structure;

forming an another contact hole penetrating the gate insulating film and the passivation film; and

forming a common pad upper electrode connected to the common pad lower electrode through the another contact hole.

10. The method according to claim 9, wherein the contact hole is extended to penetrate to a second conductive layer of the common pad lower electrode.

11. The method according to claim 1, further comprising:

forming a data pad lower electrode;

forming an another contact hole penetrating the passivation film; and

forming a data pad upper electrode connected to the data pad lower electrode through the another contact hole.

12. The method according to claim 1, wherein the gate line and the common line are formed of the first and second conductive layers and have a stepped difference.

13. The method according to claim 1, wherein the pixel electrode is formed of one of a transparent conductive layer, titanium and tungsten.

14. The method according to claim 1, wherein forming the gate pattern and the common pattern includes:

forming the first and second conductive layers on the substrate;

forming first and second photo-resist patterns having a different thickness on the second conductive layer using a photolithography process including one of a halftone mask and diffractive exposure mask;

forming the gate pattern and the common line of the double layered structure, and the common electrode where the second conductive layer remains, by patterning the first and second conductive layers using an etching process including the first and second photo-resist patterns;

forming the first photo-resist pattern thin and removing the second photo-resist pattern using an ashing process;

removing a second conductive layer on the common electrode using an etching process using the ashed first photo-resist pattern; and

removing the ashed first photo-resist pattern.