Semiconductor device, method of making the same and liquid crystal display device

• US 7,317,207 B2
• Filed: 06/07/2005
• Issued: 01/08/2008
• Est. Priority Date: 10/29/1999
• Status: Expired due to Fees

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Park, Seang-kee, Nakagawa, Kiyokazu, Sugii, Nobuyuki, Yamaguchi, Shinya, Miyao, Masanobu
• Primary Examiner(s): Purvis; Sue A.
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US11/146,016
• Publication Number:
  US 20050230683A1
• Time in Patent Office: 945 Days
• Field of Search: 257/59, 257347-355, 438/149, 438/479, 438/517
• US Class Current: 257/66
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 27/1281 by using structural features to control crystal growth, e.g. placement of grain filters
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate.

A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

Claims

1. A thin-film semiconductor device comprising an insulator, a polycrystalline layer formed on said insulator, and a transistor comprising a source region, a drain region, and a channel region formed at a surface portion of said polycrystalline layer, and a gate electrode overlying said surface portion, said polycrystalline layer comprising crystal grains of an element selected from the group of Type-IV elements and alloys thereof, said crystal grains joined with crystal grain boundaries of {111} twin of Diamond structure,

wherein said polycrystalline layer has a structure where a total of n-layers (n is 2 or larger) of semiconductor thin film are laminated, said source region, drain region, and channel region are formed at the surface of the uppermost semiconductor thin film of the n-layers of semiconductor thin film, and the gate electrode is formed at a surface of a gate insulator formed at the uppermost semiconductor thin film, the k-th (k=1 to n) semiconductor thin film has poly-crystals having a larger crystal grain size as the value of k increases and the grain boundary of the uppermost semiconductor thin film has the {111} twin of Diamond structure.

2. A thin-film semiconductor device comprising an insulator, a semiconductor thin-film formed on said insulator, and a transistor comprising a source region, a drain region, and a channel region formed at the surface of said semiconductor thin-film, and a gate electrode formed at the surface of a gate insulator formed at the surface of said semiconductor thin-film, said semiconductor thin-film having amorphous regions of Type-IV element and dendrite crystal regions of Type-IV element connecting said source region and said drain region,

wherein said semiconductor thin-film has a structure where a total of n-layers (n is 2 or larger) of semiconductor thin film are laminated, said source region, said drain region, and said channel region are formed at the surface of the uppermost semiconductor thin film of the n-layers of semiconductor thin film, and said gate electrode is formed at the surface of a gate insulator formed at the uppermost semiconductor thin film, the k-th (k=1 to n) semiconductor thin-film increases width and length of dendrite crystal as the value of k increases, and the grain boundary of the uppermost semiconductor thin-film has {111} twin of Diamond structure.