Power semiconductor device

• US 7,317,225 B2
• Filed: 10/20/2006
• Issued: 01/08/2008
• Est. Priority Date: 06/21/2004
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Omura, Ichiro, Saito, Wataru
• Primary Examiner(s): Schillinger; Laura M.
• Application Number:
  US11/551,526
• Publication Number:
  US 20070040217A1
• Time in Patent Office: 445 Days
• Field of Search: 257/341, 257/330, 257/328
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction, each of the first and second pillar layers having a column-shaped sectional structure; third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section in a device termination section and which are arranged alternately in a horizontal direction, each of the third and fourth pillar layers having a column-shaped sectional structure; an outermost pillar layer which is stacked on one of the third or fourth pillar layers in the super-junction structure of the device termination section nearest to the device section to be additionally formed to an outermost portion of the super-junction structure of the device section nearest to the device termination section and which has an impurity concentration less than that of each of the first and second pillar layers; a high resistance layer of the first conductive type which is formed on the third pillar layers and the fourth pillar layers and has a resistance value higher than that of each of the first and second pillar layers.

Claims

1. A power semiconductor device comprising:

a drain layer of a first conductive type;

first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure on said drain layer of a device section and which arranged alternately in a horizontal direction, each of said first and second pillar layers having a column-shaped sectional structure;

base layers of the second conductive type which are formed on surface portions of said second pillar layers;

source layers of the first conductive type formed on a surface portion of said base layers;

gate electrodes, each formed through a gate insulating film over a region from one of said source layers formed on the surface portion of one of said base layer to the other of said source layers formed on the surface portion of the other of said base layer adjacent to the one of said base via one of said first pillar layers;

third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section on said drain layer of a device termination section and which are arranged alternately in a horizontal direction, each of said third and fourth pillar layers having a column-shaped sectional structure;

an outermost pillar layer which is stacked on one of said third or fourth pillar layers in the super-junction structure of the device termination section nearest to the device section to be additionally formed to an outermost portion of the super-junction structure of the device section nearest to the device termination section and which has an impurity concentration less than that of each of said first and second pillar layers;

a high resistance layer of the first conductive type which is formed on said third pillar layers and said fourth pillar layers and has a resistance value higher than that of each of said first and second pillar layers and said base layers;

a source electrode which is formed to be electrically connected with said base layers and said source layers; and

a drain electrode which is formed on a back face of said drain layer.

2. The power semiconductor device according to claim 1, wherein the impurity concentration in said outermost pillar layer is 0.45 time to 0.55 time the impurity concentration of each of said first and second pillar layers.

3. The power semiconductor device according to claim 1, wherein said high resistance layer is thicker than said base layers.

4. The power semiconductor device according to claim 1, wherein the thickness of said outermost pillar layer in the horizontal direction is about half of the thickness of each of said first and second pillar in the horizontal direction.

5. The power semiconductor device according to claim 1, wherein the thickness of said high resistance layer is smaller than that of each of said first and second pillar layers in the vertical direction.

6. The power semiconductor device according to claim 1, further comprising a RESURF (Reduced Surface Field) layer formed on a surface portion of said high resistance layer.

7. The power semiconductor device according to claim 1, further comprising:

an insulating film which covers said high resistance layer, and a portion of one of said base layers positioned in a boundary portion between the device section and the device termination section; and

a field plate electrode which is formed so as to extend said source electrode up to the device termination section and cover said insulating film.

8. The power semiconductor device according to claim 7, wherein said insulating film is formed such that a film thickness thereof gradually becomes thicker toward a peripheral portion of the device.

9. The power semiconductor device according to claim 1, wherein each of said third and fourth pillar layers has an impurity concentration lower than that of each of said first and second pillar layers.

10. The power semiconductor device according to claim 1, wherein a conductive type of said outermost pillar layer is the first conductive type.

11. The power semiconductor device according to claim 1, wherein a conductive type of said outermost pillar layer is the second conductive type.