Wafer level package structure of optical-electronic device and method for making the same

• US 7,317,235 B2
• Filed: 03/18/2005
• Issued: 01/08/2008
• Est. Priority Date: 08/03/2004
• Status: Expired due to Fees

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chen, Tai-Hung, Huang, Yuan-Chang, Lin, Yao-Sheng, Lu, Su-Tsai
• Primary Examiner(s): Zarneke; David A.
• Application Number:
  US11/082,899
• Publication Number:
  US 20060030079A1
• Time in Patent Office: 1,026 Days
• Field of Search: 257/433, 257/434
• US Class Current: 257/433
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.

Claims

1. A wafer level package structure for optical-electronic devices, comprising:

a plurality of chips formed by dividing the substrate, each of which has surfaces with a plurality of optical sensitive areas and a plurality of bonding pads, the bonding pads providing electrical communication between the optical sensitive area and its exterior;

a transparent layer, whose surfaces have a plurality of conductive circuits and more than one scribe line, the substrate surface being connected to the transparent layer surface by connecting bonding pad to the conductive circuit, and the scribe line being determined according the position to each of said chips and said conductive circuits;

a protection layer, which is formed on transparent layer covering each of said chip and partially expose the conductive circuit on said transparent layer; and

a conductive film, which is formed on the protection layer and connected to the expose conductive circuit of the transparent layer.

2. The wafer level package structure of optical-electronic devices of claim 1, wherein the optical sensitive area is an array of a plurality of optical sensitive devices.

3. The wafer level package structure of optical-electronic devices of claim 1, wherein the bonding pad includes a conductive bump.

4. The wafer level package structure of optical-electronic devices of claim 1, wherein the conductive circuit includes a plurality of conductive bumps each of which is connected to the associated bonding pad.

5. The wafer level package structure of optical-electronic devices of claim 1, wherein the protection layer is a photo resist layer.