System, method, and product for scanning of biological materials employing dual analog integrators

• US 7,317,415 B2
• Filed: 08/06/2004
• Issued: 01/08/2008
• Est. Priority Date: 08/08/2003
• Status: Active Grant

• Current Assignee: Affymetrix, Inc. (Thermo Fisher Scientific Incorporated)
• Original Assignee: Affymetrix, Inc. (Thermo Fisher Scientific Incorporated)
• Inventors: Kaiser, Michael D.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US10/913,102
• Publication Number:
  US 20050059062A1
• Time in Patent Office: 1,250 Days
• Field of Search: 341/155, 341/166, 341/167, 341/169, 341/156, 250/207, 250/214.R
• US Class Current: 341/155
• CPC Class Codes: C12Q 1/6837 using probe arrays or probe chips C12Q1/6874 takes precedence
• CPC Class Codes: G01J 3/2803 using photoelectric array detector
• CPC Class Codes: G01J 3/4406 Fluorescence spectrometry
• CPC Class Codes: G01N 2021/6471 Special filters, filter wheel
• CPC Class Codes: G01N 21/274 Calibration, base line adjustment, drift correction
• CPC Class Codes: G01N 21/6428 Measuring fluorescence of fluorescent products of reactions or of fluorochrome labelled reactive substances, e.g. measuring quenching effects, using measuring "optrodes" in vivo A61B5/00; immunoassay G01N33/53
• CPC Class Codes: G01N 21/6452 Individual samples arranged in a regular 2D-array, e.g. multiwell plates

Abstract

In one embodiment, a system is described for reducing a dark period between successive data acquisition periods associated with the detection of one or more target molecules hybridized to at least one of a plurality of probes disposed upon a biological probe array. The system comprises a switch that alternately directs an analog signal between a first circuit and a second circuit, where a period of time is required to alternate between the first and second circuits; an integrator associated with the first circuit that integrates the analog signal to generate a first integrated value; a second integrator associated with the second circuit that integrates the analog signal to generate a second integrated value; and an analog/digital converter that produces a digital value for each of the first integrated value and the second integrated values.

Claims

1. A system for reducing a dark period between successive data acquisition periods associated with the detection of one or more target molecules hybridized to at least one of a plurality of probes disposed upon a biological probe array, comprising:

a switch that alternately directs an analog signal between a first circuit and a second circuit, wherein a period of time is required to alternate between the first and second circuits and the period of time includes a dark period;

a first integrator associated with the first circuit that integrates the analog signal to generate a first integrated value;

a second integrator associated with the second circuit that integrates the analog signal to generate a second integrated value; and

an analog/digital converter that produces a digital value for each of the first integrated value and the second integrated values wherein the signal from the first and second integrated values are our of phase to reduce the dark period.

2. The system of claim 1, wherein:

the analog signal includes a signal from a detector.

3. The system of claim 2, wherein:

the detector detects fluorescent emissions from labels associated with the one or more target molecules.

4. The system of claim 2, wherein:

the detector includes a photomultiplier tube.

5. The system of claim 1, wherein:

dark period is associated with the reset function of an integrator circuit.

6. The system of claim 1, wherein:

the dark period is <

20 ns.

7. The system of claim 1, wherein:

the first and second integrators each integrate the analog signal for the data acquisition period.

8. The system of claim 7, wherein:

the data acquisition period includes a period in the range of 1-100 μ

s.

9. The system of claim 7, wherein:

the data acquisition period is associated with a pixel size.

10. The system of claim 9, wherein:

the pixel size includes a range of sizes including the range of 0.4-2.5 μ

m.

11. The system of claim 1, wherein:

the first integrator and second integrator are substantially out of phase.

12. The system of claim 1, further comprising:

a buffer that receives the analog signal that creates a low impedance voltage for the first and second integrators.

13. The system of claim 1, wherein:

each digital value is associated with a pixel in an image, wherein the digital value is representative of emission intensity.

14. The system of claim 13, wherein:

the image includes a representation of at least one probe feature, wherein each probe feature includes a number of the pixels in a range of 4-144 pixels.

15. The system of claim 1, further comprising:

scanner firmware that calculates an offset correction value and a gain correction value.

16. The system of claim 15, wherein:

the scanner firmware applies the offset correction value and the gain correction value to the output of one of the first or second integrators.

17. The system of claim 15, further comprising:

an offset and gain matcher that applies the offset correction value and a gain correction value to one of the first or second integrated values.

18. The system of claim 15, wherein:

the offset correction value and the gain correction value are applied to compensate for differences between the first integrator and the second integrator.

19. The system of claim 18, wherein:

the differences are selected from the group consisting of operational amplifier characteristics, switch characteristics, and capacitor tolerances.

20. A method for reducing a dark period between successive data acquisition periods associated with the detection of one or more target molecules hybridized to at least one of a plurality of probes disposed upon a biological probe array, comprising:

alternately directing an analog signal between a first circuit and a second circuit, wherein a period of time is required to alternate between the first and second circuits and the period of time includes a dark period;

integrating the analog signal in the first circuit to generate a first integrated value;

integrating the analog signal in the second circuit to generate a second integrated value; and

producing a digital value for each of the first integrated value and the second integrated values wherein the signal from the first and second integrated values are our of phase to reduce the dark period.

21. The method of claim 20, wherein:

the analog signal includes a signal from a detector.

22. The method of claim 21, wherein:

the detector detects fluorescent emissions from labels associated with the one or more target molecules.

23. The method of claim 20, wherein:

the detector includes a photomultiplier tube.

24. The method of claim 20, wherein:

the dark period is associated with the reset fUnction of an integrator circuit.

25. The method of claim 20, wherein:

the dark period is <

20 ns.

26. The method of claim 20, wherein:

the analog signal is integrated for the data acquisition period.

27. The method of claim 26, wherein:

the data acquisition period includes a period in the range of 1-100 μ

s.

28. The method of claim 26, wherein:

the data acquisition period is associated with a pixel size.

29. The method of claim 28, wherein:

the pixel size includes a range of sizes including the range of 0.4-2.5 μ

m.

30. The method of claim 20, wherein:

the step of integrating in the first circuit and the step of integrating in the second circuit are substantially out of phase.

31. The method of claim 20, further comprising:

associating each digital value with a pixel in an image, wherein the digital value is representative of emission intensity.

32. The method of claim 31, wherein:

the image includes a representation of at least one probe feature, wherein each probe feature includes a number of the pixels in a range of 4-144 pixels.

33. The method of claim 20, further comprising:

calculating an offset correction value and a gain correction value; and

applying the offset correction value and the gain correction value to one of the first or second integrated values.

34. The method of claim 33, wherein:

the offset correction and scale correction are applied to compensate for differences between the first integrator and the second integrator.

35. The method of claim 34, wherein:

the differences are selected from the group consisting of operational amplifier characteristics, switch characteristics, and capacitor tolerances.

36. A scanner system for reducing a dark period between successive data acquisition periods associated with the detection of one or more target molecules hybridized to at least one of a plurality of probes disposed upon a biological probe array, comprising;

scanner optics and detectors comprising;

a source that provides an excitation beam;

optics that direct the excitation beam at each of the plurality of probes disposed upon the biological probe array, wherein the optics collect emissions responsive to the excitation beam; and

a detector that produces an analog signal responsive to the collected emissions from the optics; and

a computer having executable firmware stored thereon and a sensor board comprising;

a switch that alternately directs the analog signal between a first circuit and a second circuit, wherein a period of time is required to alternate between the first and second circuits;

a first integrator associated with the first circuit that integrates the analog signal to generate a first integrated value;

a second integrator associated with the second circuit that integrates the analog signal to generate a second integrated value; and

an analog/digital converter that produces a digital value for each of the first integrated value and the second integrated values.

37. A system for computing correction values between integrators comprising:

a voltage reference generator that provides a first reference voltage and a second reference voltage;

a switch that sequentially directs the first and second reference voltage between a first circuit and a second circuit;

a first integrator associated with the first circuit that sequentially integrates the first and second reference voltage to generate a first reference value and a second reference value;

a second integrator associated with the second circuit that sequentially integrates the first and second reference voltage to generate a third reference value and a fourth reference value; and

firmware that computes an offset correction value and a gain correction value, wherein the offset correction value and the gain correction value are computed from a difference between an offset value and a gain value each associated with a first linear plot based upon the first and second reference values, and a second linear plot based upon the third and fourth reference values.

38. The system of claim 37, wherein:

wherein the first reference value includes an integrated value from the first reference voltage, and the second reference value includes an integrated value from the second reference voltage.

39. The system of claim 37, wherein:

wherein the third reference value includes an integrated value from the first reference voltage, and the fourth reference value includes an integrated value from the second reference voltage.

40. The system of claim 37, wherein:

the firmware applies the offset correction value and the gain correction value to the output of one of the first or second integrators.

41. The system of claim 37, further comprising:

an offset and gain matcher that applies the offset correction value and a gain correction value to an integrated value produced by one of the first or second integrators.

42. The system of claim 41, wherein:

the integrated value is associated with a pixel in an image.

43. The system of claim 42, wherein:

the pixel is representative of fluorescent emissions, wherein the fluorescent emissions result from scanning a biological probe array.

44. A method for computing correction values between integrators comprising:

providing a first reference voltage and a second reference voltage;

sequentially directing the first and second reference voltage between a first circuit and a second circuit;

sequentially integrating the first and second reference voltage in the first circuit to generate a first reference value and a second reference value;

sequentially integrating the first and second reference voltage in the second circuit to generate a third reference value and a fourth reference value; and

computing an offset correction value and a gain correction value, wherein the offset correction value and the gain correction value are computed from a difference between an offset value and a gain value each associated with a first linear plot based upon the first and second reference values, and a second linear plot based upon the third and fourth reference values.