CMOS APS readout scheme that combines reset drain current and the source follower output

• US 7,317,484 B2
• Filed: 01/08/2004
• Issued: 01/08/2008
• Est. Priority Date: 02/26/2003
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Digital Imaging Systems GmbH
• Inventors: Levine, Peter Alan, Dosluoglu, Taner
• Primary Examiner(s): Vu, Ngoc-Yen
• Assistant Examiner(s): Peterson, Christopher K
• Application Number:
  US10/753,638
• Publication Number:
  US 20040165093A1
• Time in Patent Office: 1,461 Days
• Field of Search: 348/308, 348/241, 348/242, 348/243, 257/291, 257/292, 250/208.1, 345/98, 345/100
• US Class Current: 348/308
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A circuit and method for reducing noise in video imagers which takes advantage of the fact that the same image information is present in the drain current in a reset transistor used to reset a photodiode in a pixel as is present in the readout current. The noise is reduced by passing the multiplexed output voltage from the source follower output transistor in an APS imager system through a high pass filter to reduce the low frequency noise from the source follower. The drain current in the reset transistor used to reset the APS is passed through a low pass filter. The low pass filter output and the high pass filter output are then combined. Since the drain current in the reset transistor contains the same image information as the voltage output of the source follower output transistor the image information can be obtained by combining the output of the low pass filter and the output of the high pass filter. Since the low frequency noise components of the source follower output transistor have been suppressed combined outputs of the low pass filter and high pass filter will provide the image information with greatly suppressed low frequency noise.

Claims

1. A pixel circuit, comprising:

a photodiode having a cathode;

a reset transistor, wherein said reset transistor is a field effect transistor having a source connected to said cathode of said photodiode, and a drain;

an output transistor, wherein said output transistor is a field effect transistor having a gate connected to said cathode of said photodiode and a source;

a sample and hold circuit;

means for electrically connecting said source of said output transistor to said sample and hold circuit or electrically isolating said source of said output transistor from said sample and hold circuit;

a column select transistor, wherein said column select transistor is a field effect transistor having a drain connected to said sample and hold circuit, a gate connected to a column select input, and a source;

a first capacitor connected between and an output node and said source of said column select transistor;

a resistor connected between said output node and said drain of said reset transistor;

a second capacitor connected between said output node and ground potential.

2. The pixel circuit of claim 1 wherein the potential of said cathode of said photodiode is related to the amount of light impinging on said photodiode during a charge integration period.

3. The pixel circuit of claim 1 wherein said sample and hold circuit comprises a third capacitor and a means for resetting the amount of charge stored on said third capacitor.

4. The pixel circuit of claim 3 wherein said means for resetting the amount of charge on said third capacitor comprises a sample-hold transistor wherein said sample-hold transistor is a field effect transistor having a source and a drain connected in parallel with said third capacitor.

5. The pixel circuit of claim 1 wherein said means for electrically connecting said source of said output transistor to said sample and hold circuit or electrically isolating said source of said output transistor from said sample and hold circuit comprises a row select transistor and a sample transistor connected in series between said source of said output transistor and said sample and hold circuit, wherein said row select transistor and said sample transistor are field effect transistors.

6. The pixel circuit of claim 1 wherein a reset potential is supplied to said first output node to reset said photodiode during a reset period.

7. The pixel circuit of claim 1 wherein said output node is connected to a horizontal output buss.

8. The pixel circuit of claim 1 wherein said reset transistor is turned on, said means for electrically connecting said source of said output transistor to said sample and hold circuit or electrically isolating said source of said output transistor from said sample and hold circuit electrically isolates said source of said output transistor from said sample and hold circuit, and the potential of said cathode of said photodiode is reset during a reset period.

9. The pixel circuit of claim 1 wherein said reset transistor is turned off, said means for electrically connecting said source of said output transistor to said sample and hold circuit or electrically isolating said source of said output transistor from said sample and hold circuit electrically isolates said source of said output transistor from said sample and hold circuit, and charge is accumulated at said photodiode during a charge integration period.

10. The pixel circuit of claim 1 wherein said reset transistor is turned off, said means for electrically connecting said source of said output transistor to said sample and hold circuit or electrically isolating said source of said output transistor from said sample and hold circuit electrically connects said source of said output transistor to said sample and hold circuit, and the potential at said cathode of said photodiode is stored by said sample and hold circuit during a readout period.

11. The pixel circuit of claim 1 wherein a column select signal at said column select input of said output transistor either turns said output transistor on, thereby electrically connecting said sample and hold circuit to said second node, or turns said output transistor off, thereby electrically isolating said sample and hold circuit from said second node.

12. A pixel circuit;

comprising;

a number of sensor circuits wherein each of said sensor circuits comprises a photodiode having a cathode, a reset transistor having a source connected to said cathode of said photodiode and a drain, an output transistor having a gate connected to said cathode of said photodiode and a source, a sample and hold circuit, a row select transistor and a sample transistor connected in series between said source of said output transistor and said sample and hold circuit, a column select transistor having a drain connected to said sample and hold circuit and a source;

a first node connected to an output node;

a second node connected to each of said drains of each of said reset transistors of each of said sensor circuits;

a resistor connected between said first node and said second node

a filter capacitor connected between said first node and each of said sources of each of said column select transistors of each of said sensor circuits; and

an output capacitor connected between said first node and ground potential.

13. The pixel circuit of claim 12 wherein said reset transistors, said sample transistors, said row select transistors, said output transistors, and said column select transistors are field effect transistors.

14. The pixel circuit of claim 12 wherein said number of sensor circuits is four sensor circuits.

15. The pixel circuit of claim 12 wherein the potential of said cathode of each of said photodiodes at the end of a charge integration period is related to the amount of light impinging on that said photodiode during said charge integration period.

16. The pixel circuit of claim 12 wherein each of said sample and hold circuits comprise a sample-hold capacitor and a means for resetting the amount of charge stored on said sample-hold capacitor.

17. The pixel circuit of claim 16 wherein said means for resetting the amount of charge on said sample-hold capacitor comprises a sample-hold transistor wherein said sample-hold transistor is a field effect transistor having a source and a drain connected in parallel with said sample-hold capacitor.

18. The pixel circuit of claim 12 wherein a reset potential is supplied to said second node and each of said reset transistors are turned on to reset each of said photodiodes during a reset period.

19. The pixel circuit of claim 12 wherein at the completion of a charge integration period each of said row select transistors are turned on, each of said sample transistors are turned on, and a potential related to the charge accumulated at each photodiode of each said sensor circuit during said charge integration period is stored by said sample and hold circuit of each said sensor circuits.

20. The pixel of claim 12 wherein during a reset period a reset potential is supplied to said second node and each of said reset transistors are turned on thereby causing a reset current to flow from said second node into each of said reset transistors, and each of said column select transistors are turned on sequentially thereby causing a signal current related to a potential stored by said sample and hold circuit of each of said sensor circuits to flow from said source of each of said column select transistors to said first node.

21. A method of reading an active pixel sensor;

comprising;

providing a number of sensor circuits wherein each of said sensor circuits comprises a photodiode having a cathode, a reset transistor having a source connected to said cathode of said photodiode and a drain, an output transistor having a gate connected to said cathode of said photodiode and a source, a sample and hold circuit, a row select transistor and a sample transistor connected in series between said source of said output transistor and said sample and hold circuit, a column select transistor having a drain connected to said sample and hold circuit and a source;

providing a first node connected to an output node;

providing a second node connected to each of said drains of each of said reset transistors of each of said sensor circuits;

providing a filter capacitor connected between said first node and each of said sources of each of said column select transistors of each of said sensor circuits;

providing an output capacitor connected between said first node and ground potential;

providing a resistor connected between said second node and said first node;

turning off said reset transistor said sample transistor, and accumulating charge on each of said photodiodes in each of said sensor circuits during a charge integration period;

turning off said reset transistors, turning on said sample transistors, turning on said row select transistors and storing a signal at each of said sample and hold circuits in each of said sensor circuits after said charge integration period has been completed, wherein said signal stored at said sample and hold circuit in each of said sensor circuits is related to the potential of said cathode of said photodiode in that said sensor circuit after said charge integration period has been completed; and

turning on said reset transistors, turning off said sample transistors, and sequentially turning on each of said column select transistors after storing said signal at each of said sample and hold circuits in each of said sensor circuits;

thereby causing a reset current to flow from said second node to each of said drains of each of said reset transistors, signal currents to flow from each of said sample and hold circuits into said first node, and providing an output signal to said horizontal bus comprising low frequency components of said reset current mixed with high frequency components of said signal currents.

22. The method of claim 21 wherein said reset transistors, said sample transistors, said row select transistors, said output transistors, and said column select transistors are field effect transistors.

23. The method of claim 21 wherein said number of sensor circuits is four sensor circuits.

24. The method of claim 21 wherein the potential of said cathode of each of said photodiodes at the end of said charge integration period is related to the amount of light impinging on that said photodiode during said charge integration period.

25. The method of claim 21 wherein each of said sample and hold circuits comprise a sample-hold capacitor and a means for resetting the amount of charge stored on said sample-hold capacitor.

26. The method of claim 25 wherein said means for resetting the amount of charge on said sample-hold capacitor comprises a sample-hold transistor wherein said sample-hold transistor is a field effect transistor having a source and a drain connected in parallel with said sample-hold capacitor.

27. The method of claim 21 wherein after storing said signal at each of said sample and hold circuits in each of said sensor circuits a reset potential is supplied to said second node and each of said reset transistors are turned on thereby causing said reset current to flow from said second node into each of said drains of said reset transistors.