Protection of NROM devices from charge damage

• US 7,317,633 B2
• Filed: 07/05/2005
• Issued: 01/08/2008
• Est. Priority Date: 07/06/2004
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Lusky, Eli, Bloom, Ilan, Shappir, Assaf, Eitan, Boaz
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US11/175,801
• Publication Number:
  US 20060007612A1
• Time in Patent Office: 917 Days
• Field of Search: 365/185.03, 365/185.09, 365/185.2, 365/185.23, 257/357, 257/356, 257/355, 257/324, 257/173, 438/261, 438/591, 438/593
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.

Claims

1. A method for protecting NROM devices from charge damage during process steps, the method comprising:

providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor (T1) and an NMOS transistor (T4), the PMOS transistors (T1) sharing a common deep N well and the NMOS transistors (T4) connected to a P well, providing an N+ tap connected to said N well and connecting the N+ tap to a positive voltage clamping device; and

connecting all the P wells together to a common P+ taps, connecting the P+ tap to a negative voltage clamping device;

wherein during process steps, the negative and positive voltage clamping devices direct leakage current to a ground potential;

providing antenna structure and at least one access transistor for protection during top-level metal formation, and wherein said antenna structure comprises a dummy word line connected to a word line driver.

2. The method according to claim 1, wherein said negative voltage clamping device comprises a NMOS transistor (T5).

3. The method according to claim 1, wherein said positive voltage clamping device comprises a PMOS transistor (T2).

4. The method according to claim 1, further comprising providing at least one access transistor for access of voltage bias to the clamping devices during operation mode.

5. The method according to claim 1, wherein for negative charging protection structure comprising NMOS transistors (T4) and (T5), the at least one access transistor is an NMOS transistor (T6).

6. The method according to claim 1, wherein for positive charging protection structure comprising PMOS transistors (T1) and (T2), the at least one access transistor is a PMOS transistor (T3).

7. The method according to claim 1, wherein all the P wells are connected together with a first metal layer.

8. The method according to claim 1, wherein all the P wells are connected together with a poly layer.

9. The method according to claim 1, wherein the P well is a common P well.

10. Circuitry for protecting NROM devices from charge damage during process steps, the circuitry being used with existing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, an PMOS transistor (T1) and a NMOS transistor (T4), the PMOS transistors (T1) sharing a common deep N well and the NMOS transistors (T4) each connected to a P well, the circuitry comprising:

an N+ tap connected to said N well and to a positive voltage clamping device, a common P+ tap that connects all the P wells together, the common P+ tap being connected to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground potential;

providing antenna structure and at least one access transistor for protection during top-level metal formation, and wherein said antenna structure comprises a dummy word line connected to a word line driver.

11. The circuitry according to claim 10, wherein said negative voltage clamping device comprises an NMOS transistor (T5).

12. The method circuitry according to claim 10, wherein said positive voltage clamping device comprises a PMOS transistor (T2).

13. The method circuitry according to claim 10, further comprising providing at least one access transistor for access of voltage bias to the clamping devices during operation mode.