DC offset cancel circuit

• US 7,317,904 B2
• Filed: 12/22/2004
• Issued: 01/08/2008
• Est. Priority Date: 12/25/2003
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Aida, Tomio, Uramoto, Yasutaka, Matsushita, Masatoshi
• Primary Examiner(s): LE, THANH C
• Application Number:
  US11/019,033
• Publication Number:
  US 20050143032A1
• Time in Patent Office: 1,112 Days
• Field of Search: None
• US Class Current: 455/232.1
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A DC offset cancel circuit includes an analog adder 1 to whose one input a baseband analog signal output from a high-frequency reception section is input and to whose other input an analog correction signal output from a D/A converter 7 is input, and which corrects the reference voltage value of the baseband analog signal analogically to cancel a DC offset, an adder 3 which has the output of the A/D converter 2 as its one input and subtracts the lower bits of a sample value stored in a memory 6 to be described later as a DC offset value from the input value and outputs the resultant value, a control circuit 5 which outputs an output digital value of the A/D converter 2 as a sample value to the memory 6, and a D/A converter 7 which converts a digital value of the upper bits of a sample value stored in the memory 6 to an analog correction signal and outputs the analog correction signal to the analog adder 1.

Claims

1. A DC offset cancel circuit including:

an analog adder which subtracts, from a baseband analog signal input to one end, an analog correction signal input from the other end;

an A/D converter which converts an output of the analog adder to a digital value;

a control circuit which extracts an output digital value of the A/D converter as a sample value;

a control section which controls an operation timing of the control circuit;

a memory which stores the sample value;

a D/A converter which converts upper bits of the sample value to an analog value and outputs the analog value as the analog correction signal to the analog adder; and

an adder which subtracts, from an output of the A/D converter input to one end, lower bits of the sample value input from the other end.

2. The DC offset cancel circuit according to claim 1, wherein the control circuit is an averaging circuit which acquires an average value of an output digital value of the A/D converter.

3. The DC offset cancel circuit according to claim 1 or 2, wherein the control section sets a DC offset detection zone of the baseband analog signal as the operation timing.

4. The DC offset cancel circuit according to claim 1 or 2, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the adder.

5. The DC offset cancel circuit according to claim 1 or 2, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the A/D converter.

6. The DC offset cancel circuit according to claim 1 or 2, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the analog adder.

7. The DC offset cancel circuit according to claim 1 or 2, including a determination section which performs timing control of the control circuit in a noise zone determined from the baseband analog signal.

8. A DC offset cancel circuit including:

an A/D converter having an analog adder and a D/A converter for feeding back an analog signal for digital conversion to the analog adder, in which the analog adder subtracts, from a baseband analog signal input to one end, an analog correction signal input from the other end;

a control circuit which extracts an output digital value of the A/D converter as a sample value;

a control section which controls an operation timing of the control circuit;

a memory which stores the sample value;

a D/A converter which converts an output digital value of the A/D converter input to one end and upper bits of the sample value input to the other end to an analog value and outputs the analog value as the analog correction signal to the analog adder; and

an adder which subtracts, from an output digital value of the A/D converter input to one end, lower bits of the sample value input from the other end.

9. The DC offset cancel circuit according to claim 8, wherein the A/D converter is a high-order converter.

10. The DC offset cancel circuit according to claim 9, including a correction section which performs an arithmetic processing on the upper bits of the sample value.

11. The DC offset cancel circuit according to any one of claims 8 to 10, wherein the D/A converter which outputs the correction signal to the analog adder has a shared structure.

12. The DC offset cancel circuit according to claim 8, wherein the A/D converter has a digital filter.

13. The DC offset cancel circuit according to claim 8, wherein the control circuit is an averaging circuit which acquires an average value of an output digital value of the A/D converter.

14. The DC offset cancel circuit according to claim 8, wherein the control section sets a DC offset detection zone of the baseband analog signal as the operation timing.

15. The DC offset cancel circuit according to claim 8, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the adder.

16. The DC offset cancel circuit according to claim 8, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the A/D converter.

17. The DC offset cancel circuit according to claim 8, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the analog adder.

18. The DC offset cancel circuit according to claims 8, including a determination section which performs timing control of the control circuit in a noise zone determined from the baseband analog signal.

19. A DC offset cancel circuit including:

an analog adder which subtracts, from a baseband analog signal input to one end, an analog correction signal input from the other end;

an integrator which integrates an output of the analog adder;

a quantizer which quantizes an output of the integrator;

a control circuit which extracts an output digital value of the quantizer as a sample value;

a control section which controls an operation timing of the control circuit;

a memory which stores the sample value;

a 2-input D/A converter which converts an output digital value of the quantizer input to one end and upper bits of the sample value input to the other end to an analog value and outputs the analog value as the analog correction signal to the analog adder; and

an adder which subtracts, from an output digital value of the quantizer input to one end, lower bits of the sample value input from the other end.

23. The DC offset cancel circuit according to any one of claims 19 to 22, wherein the 2-input D/A converter has an adder which adds an output of the quantizer to a digital value corresponding to upper bits of the memory, and a D/A converter which converts an output of the adder to an analog signal.

24. The DC offset cancel circuit according to any one of claims 19 to 22, wherein the 2-input D/A converter has a D/A converter which converts an output digital value of the quantizer to an analog value, a D/A converter which converts a digital value corresponding to upper bits of the memory to an analog value, and an adder which adds outputs of the D/A converters.

25. The DC offset cancel circuit according to any one of claims 19 to 22, including a digital filter provided between the quantizer and the adder.

26. The DC offset cancel circuit according to any one of claims 19 to 22, wherein the control circuit is an averaging circuit which acquires an average value of output digital values of the quantizer.

27. The DC offset cancel circuit according to any one of claims 19 to 22, wherein the control section sets a DC offset detection zone of the baseband analog signal as the operation timing.

28. The DC offset cancel circuit according to any one of claims 19 to 22, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the adder.

29. The DC offset cancel circuit according to any one of claims 19 to 22, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the quantizer.

30. The DC offset cancel circuit according to any one of claims 19 to 22, including a determination section which performs timing control of the control circuit in a noise zone determined from an output signal of the analog adder.

31. The DC offset cancel circuit according to any one of claims 19 to 22, including a determination section which performs timing control of the control circuit in a noise zone determined from the baseband analog signal.

20. A DC offset cancel circuit including:

a first analog adder which subtracts, from a baseband analog signal input to one end, an analog correction signal input from the other end;

a first integrator which integrates an output of the first analog adder;

a second analog adder which subtracts, from an output of the first integrator input to one end, an analog signal input from the other end;

a second integrator which integrates an output of the second analog adder;

a quantizer which quantizes an output of the second integrator;

a control circuit which extracts an output digital value of the quantizer as a sample value;

a control section which controls an operation timing of the control circuit;

a memory which stores the sample value;

a 2-input D/A converter which converts an output digital value of the quantizer input to one end and upper bits of the sample value input to the other end to an analog value and outputs the analog value as the analog correction signal to the first analog adder;

a D/A converter which converts an output digital value of the quantizer to an analog value and outputs the analog value to the second analog adder; and

an adder which subtracts, from an output digital value of the quantizer input to one end, lower bits of the sample value input from the other end.

21. A DC offset cancel circuit including:

a first analog adder which subtracts, from a baseband analog signal input to one end, an analog signal input from the other end;

a first integrator which integrates an output of the first analog adder;

a second analog adder which subtracts an analog correction signal from an output of the first integrator input to one end;

a second integrator which integrates an output of the second analog adder;

a quantizer which quantizes an output of the second integrator;

a control circuit which extracts an output digital value of the quantizer as a sample value;

a control section which controls an operation timing of the control circuit;

a memory which stores the sample value;

a correction section which performs an arithmetic processing on upper bits of the sample value;

a D/A converter which converts an output digital value of the quantizer to an analog value and outputs the analog value to the first analog adder;

a 2-input D/A converter which converts an output digital value of the quantizer input to one end and an output digital value of the correction section input to the other end to an analog value and outputs the analog value as the analog correction signal to the second analog adder; and

an adder which subtracts, from an output digital value of the quantizer input to one end, lower bits of the sample value input from the other end.

22. A DC offset cancel circuit including:

a first analog adder which subtracts, from a baseband analog signal input to one end, a first analog correction signal input from the other end;

a first integrator which integrates an output of the first analog adder;

a second analog adder which subtracts a second analog correction signal from an output of the first integrator;

a second integrator which integrates an output of the second analog adder;

a quantizer which quantizes an output of the second integrator;

a control circuit which extracts an output digital value of the quantizer as a sample value;

a control section which controls an operation timing of the control circuit;

a memory which stores the sample value;

a dividing section which divides upper bits of the sample value to first and second upper bits;

a correction section which performs an arithmetic processing on the second upper bits output from the dividing section;

a first 2-input D/A converter which converts an output digital value of the quantizer input to one end and the first upper bits output from the dividing section and input to the other end to an analog value and outputs the analog value as the first analog correction signal to the first analog adder;

a second 2-input D/A converter which converts an output digital value of the quantizer input to one end and an output digital value of the correction section input to the other end to an analog value and outputs the analog value as the second analog correction signal to the second analog adder; and

an adder which subtracts, from an output of the quantizer input to one end, lower bits of the sample value input from the other end.