Hardware assisted communication between processors

• US 7,318,120 B2
• Filed: 12/24/2004
• Issued: 01/08/2008
• Est. Priority Date: 07/19/2002
• Status: Expired due to Term

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Rust, Robert A., Cohen, Eugene M., McLean, Scott D.
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US11/023,091
• Publication Number:
  US 20050120190A1
• Time in Patent Office: 1,110 Days
• Field of Search: None
• US Class Current: 711/114
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99955 Archiving or backup

Abstract

A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor to read the information from a second block of mirrored memory. The information is saved in memory accessible to a second processor. The information is accessed by the second processor.

Claims

1. A method of performing hardware assisted communication between processors, comprising:

in response to direction from a first processor, using a first coprocessor to write information in a first block of mirrored memory;

maintaining mirrored memory;

reading, with a second coprocessor, the information from a second block of mirrored memory;

saving the information in memory accessible to a second processor; and

accessing the information with the second processor, wherein accessing the information with the second processor comprises using dispatcher code resident within operating system code executed by the second processor.

2. The method of claim 1, additionally comprising marshalling the information with the first coprocessor.

3. The method of claim 1, additionally comprising de-marshalling the information with the second coprocessor.

4. The method of claim 1, additionally comprising:

configuring the second coprocessor to be a queue producer;

configuring the second processor to be a queue consumer; and

configuring a queue to allow the second coprocessor to write to the queue and to allow the second processor to read from the queue.

5. A method of configuring a plurality of groups, each group containing a processor, a coprocessor and an ASIC (application specific inteqrated circuit), to share work, the method comprising:

transferring information between coprocessors through the ASIC with which each coprocessor is grouped, using a bus over which the ASICs are connected;

for each group, configuring a single producer/single consumer queue, wherein the coprocessor is the single producer and the processor is the single consumer;

removing information from the single producer/single consumer queue, wherein accessing the information with the second processor comprises using dispatcher code resident within operating system code executed by the second processor; and

processing the information using software configured for operation on each processor.

6. The method of claim 5, wherein removing information from the single producer/single consumer queue comprises:

maintaining mirrored memory by passing information between a plurality of ASICs, wherein each ASIC is associated with each of a plurality of sections of the mirrored memory; and

transferring information between coprocessors using mirrored memory, wherein the information is marshaled before being saved into a first section of mirrored memory by a first coprocessor and de-marshaled after being read from a second section of mirrored memory by a second coprocessor.

7. The method of claim 5, wherein the software configured for operation on each processor is selected from among a group comprising:

front code, configured to control the operation of input/output processors;

middle code configured to control operation of a RAID device; and

back code configured to control disk drive operation.

8. A processor-readable medium, comprising processor-executable instructions for transferring information between a first processor and a second processor, the processor-executable instructions comprising processor-executable instructions for:

in response to direction from the first processor, using a first coprocessor to write information in a first block of mirrored memory;

maintaining mirrored memory by associating an array ASIC with each block of mirrored memory and by providing communication between the array ASICs associated with each mirrored memory block;

reading, with a second coprocessor, the information from a second block of mirrored memory;

saving the information into a queue defined in memory local to the second processor; and

accessing the information with the second processor.

9. The processor readable media of claim 8, additionally comprising processor-executable instructions for marshalling the information with the first coprocessor.

10. The processor readable media of claim 9, additionally comprising processor-executable instructions for de-marshalling the information with the second coprocessor.

11. The processor readable media of claim 8, wherein accessing the information with a second processor comprises additional processor-executable instructions for using dispatcher code resident within operating system code executed by the second processor to access the information.

12. The processor readable media of claim 8, additionally comprising processor-executable instructions for:

configuring the second coprocessor to be a queue producer;

configuring the second processor to be a queue consumer; and

configuring the queue within memory managed by the operating system to which the coprocessor can write and the processor can read.