Reuseable configuration data

• US 7,318,143 B2
• Filed: 01/28/2005
• Issued: 01/08/2008
• Est. Priority Date: 10/20/2004
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.), University of Michigan
• Original Assignee: Arm Limited (SoftBank Group Corp.), University of Michigan
• Inventors: Biles, Stuart D., Flautner, Krisztian, Clark, Nathan, Mahlke, Scott
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US11/044,734
• Publication Number:
  US 20060095720A1
• Time in Patent Office: 1,075 Days
• Field of Search: 712/10, 712/13, 712/15, 712/216
• US Class Current: 712/10
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis
• CPC Class Codes: G06F 8/44 Encoding
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store operable to store operand values and an accelerator having a plurality of functional units. The accelerator executes a combined operation corresponding to a computational sub-graph of the separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with the combined operation. The accelerator executes the combined operation in dependence upon operand mapping data providing a mapping between operands of the combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between the plurality of functional units and the particular processing operations. The configuration data can be re-used for different operand mappings.

Claims

1. An information processor for executing a program comprising a plurality of separate program instructions:

processing logic operable to individually execute said separate program instructions of said program;

an operand store operable to store operand values; and

an accelerator having an array comprising a plurality of functional units, said accelerator being operable to execute a combined operation corresponding to a computational subgraph of said separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with one or more processing stages of said combined operation;

wherein said accelerator executes said combined operation in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.

2. An information processor according to claim 1, in which said operand store is a register file and said storage locations of said operand mapping data are register locations.

3. An information processor according to claim 1, in which said operand store is an operand stack and said storage locations of said operand mapping data are operand stack locations.

4. An information processor according to claim 1, in which said program comprises subgraph identification information for identifying said computational subgraphs to be executed by said accelerator.

5. An information processor according to claim 4, in which said computational subgraph identification information comprises a marker instruction.

6. An information processor according to claim 1, in which at least a portion of said configuration data is generated statically prior to execution of said program.

7. An information processor according to claim 1, in which at least a portion of said configuration data is dynamically generated at runtime.

8. An information processor according to claim 5, in which said marker instruction is a branch link instruction.

9. An information processor according to claim 8, in which said branch link instruction has a field for specifying a target address enabling said separate program instructions corresponding to said computational subgraph and to be executed by said accelerator to be called as a subroutine.

10. An information processor according to claim 5, in which said marker instruction has a field for specifying a pointer to said operand mapping data.

11. An information processor according to claim 5, in which said marker instruction has at least one field for inline specification of said operand mapping data.

12. An information processor according to claim 5, in which said marker instruction has a field for specifying a pointer to said configuration data.

13. An information processor according to claim 12, in which said information processor comprises a memory operable to store said configuration data and in which said accelerator is operable to access said configuration data from said memory.

14. An information processor according to claim 12, in which said information processor is operable to reconstruct said configuration data corresponding to a particular computational subgraph from both configuration data for a different computational subgraph and configuration difference data specifying differences between configuration data for said different subgraph and configuration data for said particular computational subgraph.

15. An information processor according to claim 11, in which said information processor comprises an instruction pipeline.

16. An information processor according to claim 15, in which said accelerator is non-pipelined.

17. An information processor according to claim 15, in which at least a portion of said configuration data is generated at a decode stage of said instruction pipeline.

18. An information processor according to claim 15, comprising a trace cache and in which said configuration data is generated in dependence upon information derived from said trace cache.

19. An information processor according to claim 15, in which said information processor is operable to read said configuration data from memory and to configure said accelerator between a decode pipeline stage and an execute pipeline stage.

20. An information processor according to claim 1, in which said separate program instructions are RISC instructions and said combined operation is a CISC instruction.

21. An information processor according to claim 1, in which said operand mapping data specifies data storage locations corresponding to input operands and output operands for said computational subgraph and excludes data storage locations corresponding to intermediate results of said combined operation.

22. A method of processing information under the control of a computer program comprising a plurality of separate program instructions, said method comprising:

individually executing said separate program instructions of said program using processing logic;

storing operand values in an operand store;

executing a combined operation corresponding to a computational subgraph of said separate program instructions using an accelerator having an array comprising a plurality of functional units by configuring individual ones of said plurality of functional units to perform particular processing operations associated with one or more processing stages of said combined operation; and

executing said combined operation on said accelerator in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.

23. A computer program product comprising a computer readable storage medium containing computer readable instructions that when executed are operable to compile a source code sequence comprising a plurality of separate program instructions of a computer program to form executable program instructions, said computer program comprising:

analysis code for analysing said source code and translating said source code into a stream of executable program instructions capable of execution by processing logic within a data processing apparatus;

identifying code for identifying candidate computational subgraphs within said stream of executable program instructions;

subset selection code for selecting a subset of said candidate computational subgraphs for accelerated execution as respective combined operations on an accelerator having an array comprising a plurality of functional units, individual ones of said functional units being configurable to perform particular processing operations associated with one or more stages of said combined operations, said accelerator being operable to execute said combined operations in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said operand store and in dependence upon separately specified configuration data; and

configuration data generating code for generating said configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.

24. A method of compiling a source code sequence comprising a plurality of separate program instructions of a computer program to form executable program instructions, said method comprising:

analysing said source code sequence and translating said source code sequence into a stream of executable program instructions capable of execution by processing logic within a data processing apparatus;

identifying candidate computational subgraphs within said stream of executable program instructions;

selecting a subset of said candidate computational subgraphs for accelerated execution as respective combined operations on an accelerator having an array comprising a plurality of functional units, individual ones of said functional units being configurable to perform particular processing operations associated with one or more stages of said combined operations, said accelerator being operable to execute said combined operations in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said operand store and in dependence upon separately specified configuration data; and

generating configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.

25. An information processor for executing a program comprising a plurality of separate program instructions:

means for processing operable to individually execute said separate program instructions of said program;

means for storing operand values; and

means for accelerating execution having an array comprising a plurality of functional units, said accelerating means being operable to execute a combined operation corresponding to a computational subgraph of said separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with one or more processing stages of said combined operation;

wherein said accelerating means executes said combined operation in dependence upon operand mapping data providing a mapping between operands of said combined operation and storage locations within said storing means and in dependence upon separately specified configuration data providing a mapping between said plurality of functional units and said particular processing operations such that said configuration data can be re-used for different operand mappings.