Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays
First Claim
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1. A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs), comprising:
- placing new logic elements (LEs) at preferred locations on a layout of an existing system; and
resolving illegalities in placement of the new LEs by generating a proposed move for an LE, generating cost function values for a current placement and a placement with the proposed move, and accepting the proposed move if its associated cost function value is better than the cost function value of the current placement.
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Abstract
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes placing new logic elements (LEs) at preferred locations on a layout of an existing system. Illegalities in placement of the new LEs are resolved.
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Citations
26 Claims
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1. A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs), comprising:
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placing new logic elements (LEs) at preferred locations on a layout of an existing system; and resolving illegalities in placement of the new LEs by generating a proposed move for an LE, generating cost function values for a current placement and a placement with the proposed move, and accepting the proposed move if its associated cost function value is better than the cost function value of the current placement.
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2. A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs), comprising:
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placing new logic elements (LEs) at preferred locations on a layout of an existing system; and resolving illegalities in placement of the new LEs by generating proposed moves for an LE, generating cost function values for a current placement and placements with the proposed moves, and accepting a proposed move if its associated cost function value is better than the cost function value for the current placement. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for designing a system on field programmable gate array (FPGAs), comprising:
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determining placement of logic elements (LEs) for an existing system; modifying a design for the existing system to improve performance by estimating routing delays for the existing system, and adding LEs to the existing system to reduce the routing delays; placing new LEs from a modified design on the placement of LEs for the existing system; and resolving illegalities in placement of the new LEs.
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18. A method for designing a system on field programmable gate array (FPGAs), comprising:
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determining placement of logic elements (LEs) for an existing system; modifying a design for the existing system to improve performance; placing new LEs from a modified design on the placement of LEs for the existing system; and resolving illegalities in placement of the new LEs by generating proposed moves for an LE, generating cost function values for a current placement and placements with the proposed moves, and accepting a proposed move if its associated cost function value is better than a cost function value for the current placement. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A machine-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions which, when executed by a processor, causes the processor to perform:
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placing new logic elements (LEs) at preferred locations on a layout of an existing system; and resolving illegalities in placement of the new LEs by generating proposed moves for an LE, generating cost function values for a current placement and placements with the proposed moves, and accepting a proposed move if its associated cost function value is better than the cost function value for the current placement. - View Dependent Claims (25, 26)
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Specification