Method and system for modeling wiring routing in a circuit design

• US 7,318,212 B2
• Filed: 09/22/2005
• Issued: 01/08/2008
• Est. Priority Date: 09/22/2005
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Heymann, Omer, Noy, Gil, Amit, Niv, Speiser, Maya, Bustin, Ronit, Leibowitz, Moshe, Goren, Lidor, Raphayevich, Alex
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/232,747
• Publication Number:
  US 20070067750A1
• Time in Patent Office: 838 Days
• Field of Search: 716/2, 716/11, 716/12
• US Class Current: 716/113
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “Π”-type filter arrangement, wherein n=1, 2, 3, . . . , }. Several length ranges may be predefined to associate each segment, or path, with a particular type of wire model object.

Claims

1. A method for modeling an interconnection wiring routing having a known geometry, the method comprising defining a wire model strategy and automatically replacing said wiring routing geometry in a circuit schematic with one or more wire model objects based on said wire model strategy,

wherein said wiring routing geometry is defined by a cluster consisting of one or more source points and one or more target points and by segments interconnecting said points in a known path, and wherein the wire model strategy comprises selecting one or more wire model objects based on a predefined set of selection rules, and replacing one or more of said segments and/or paths with said one or more selected wire model objects,

wherein the wire model strategy comprises inserting the selected wire model objects into the wiring routing geometry per groups of sequential of said segments, wherein

further comprising summing the length of said sequential segments along one or more, not overlapping, of said paths between corresponding pairs of said source and target points, and, for each of said pairs of points, inserting therebetween a selected wire model object.

2. The method according to claim 1, wherein selecting one or more wire model objects comprise selecting a wire model object from a group consisting of:

a capacitor (C);

one resistor-capacitor (RC) arrangement;

a plurality (n) of Π

-type filters arrangement, wherein n=1, 2, 3 . . . , based on the predefined set of selection rules.

3. The method according to claim 1, wherein the predefined set of selection rules comprises associating a segment or path length to one of a plurality of predefined length ranges,

wherein the predefined set of selection rules comprises selecting a segment or path length based on a length ‘

l’

that is selectable from the group of lengths consisting of;

l=L<sub>longest—

path</sub>;

l=L<sub>longest—

path±

x %</sub>;

l=L<sub>average—

path</sub>;

l=L<sub>average—

path</sub>±

x %.

4. The method according to claim 3, wherein the predefined set of selection rules further comprises factoring in spacing between adjacent segments, wire metal type, and wire width.

5. A computer program product which comprises a computer useable medium that includes a computer readable program, said computer readable program, when executed on a computer, causes said computer to model an interconnection wiring routing having a known geometry by defining a wire model strategy and automatically replacing said wiring routing geometry in a circuit schematic with one or more wire model objects based on said wire model strategy, wherein said wiring routing geometry is defined by a cluster consisting of one or more source points and one or more target points and by segments interconnecting said points in a known path, and the wire model strategy includes selecting one or more wire model objects based on a predefined set of selection rules, and replacing one or more of said segments and/or paths with said one or more of the selected wire model objects, wherein the wire model strategy includes insertion of the selected wire model objects into the wiring routing geometry per groups of sequential of said segments,

wherein the wire model strategy further includes summing the length of said sequential segments along one or more, not overlapping, of said paths between corresponding pairs of said source and target points, and, for each of said pairs of points, inserting therebetween a selected wire model object.

6. A system for modeling an interconnection wiring routing having a known geometry, comprising:

a) an input memory for storing therein data relating to a wiring routing geometry of a signal path in an electric circuit design, said wiring routing geometry defined by a cluster consisting of one or more source points and one or more target points, and by line segments that interconnect said points;

b) a model decision maker for deciding one or more wire model objects to replace said segments, said model decision maker comprising;

i. a decision element, and;

ii. a storage array for storing therein said wire model objects and a set of selection rules that depends on a preferred wire model strategy;

wherein said decision element is to model the wiring routing geometry stored in said input memory in whole or in part, by automatically replacing, in the-circuit schematic, one or more of said segments with one or more of said wire model objects, based on the wire model strategy and the selection rules,

wherein the wire model strategy includes insertion of wire model objects into the wiring routing geometry per groups of sequential of said segments

wherein the wire model strategy further includes summing lengths of sequential of said segments along one or more, not overlapping, of said signal paths between corresponding pairs of said source and target points, and, for each of said pairs of points, inserting there between a wire model object of said wire model objects.