Vertically stacked field programmable nonvolatile memory and method of fabrication

• US 7,319,053 B2
• Filed: 02/14/2006
• Issued: 01/15/2008
• Est. Priority Date: 11/16/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek
• Primary Examiner(s): Vu; David
• Application Number:
  US11/355,214
• Publication Number:
  US 20060141679A1
• Time in Patent Office: 700 Days
• Field of Search: 438128-132, 438/197, 438/210, 438/467, 438600-601, 257/50, 257/530, 257/E23.147, 257/E23.149
• US Class Current: 438/131
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Claims

1. A process for fabricating a 3-D semiconductor memory device comprising the steps of:

forming a first stack comprising a P-N diode and a state change element;

forming a second stack comprising a P-N diode and a state change element overlying the first stack,

wherein the first and second stacks comprise elements of a pillar in a 3-D memory array, wherein the 3-D memory array comprises a plurality of layers of memory cells stacked vertically above one another, and

forming edge regions on the pillar using a plasma oxidation process.

2. The process of claim 1, wherein forming a first stack comprises:

forming a bottom conductor layer;

forming a bottom semiconductor layer overlying the conductor layer;

oxidizing at least a portion of the bottom semiconductor layer in a plasma to form an oxide layer thereon;

forming a top semiconductor layer overlying the oxide layer; and

sequentially etching the top semiconductor layer, the oxide layer, the bottom semiconductor layer and the bottom conductor layer.

3. A process for fabricating a pillar in a 3-D semiconductor memory device, wherein the pillar includes a P-N diode and a state change element vertically arranged between orthogonally disposed conductors leads, the process comprising the steps of:

forming a semiconductor layer; and

oxidizing at least a portion of the semiconductor layer in a plasma to form an oxide antifuse layer overlying the semiconductor layer;

wherein the 3-D semiconductor memory device comprises a plurality of layers of memory cells stacked vertically above one another.