Parallel equalization for systems using time division multiple access

• US 7,319,719 B1
• Filed: 06/21/2000
• Issued: 01/15/2008
• Est. Priority Date: 06/21/2000
• Status: Expired due to Fees

• Current Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.), ADC Telecommunications Incorporated (TE Connectivity Limited)
• Original Assignee: ADC Telecommunications Incorporated (TE Connectivity Limited)
• Inventors: Farlow, Charles S.
• Primary Examiner(s): Odom; Curtis B.
• Application Number:
  US09/598,870
• Time in Patent Office: 2,764 Days
• Field of Search: 375229-236, 375/14, 375/102
• US Class Current: 375/229
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 2025/03547 Switching between time domain structures
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

An equalization circuit is provided. The equalization circuit includes an input adapted to receive signals from a communications channel. The equalization circuit further includes a plurality of equalizer circuits coupled to the input and operable to generate a plurality of intermediate signals. A selector circuit is also included. The selector circuit is responsive to the plurality of equalizer circuits and selects one of the intermediate signals. The equalization circuit also includes an output coupled to the selector circuit that receives the selected intermediate signal.

Claims

1. An equalization circuit, comprising:

an input adapted to receive signals from a communication channel;

an equalizer bank having at least two equalizers coupled in parallel and coupled to the input;

a first decoder bank having at least two packet decoder circuits coupled in parallel, each packet decoder circuit responsive to a corresponding one of the at least two equalizers of the equalizer bank;

a selector circuit coupled to the decoder bank that selects an output signal of one of the at least two equalizer circuits based on processing of the decoder bank;

an output coupled to the selector circuit that receives the selected output signal; and

a second decoder bank having at least two error correction decoder circuits coupled in parallel, each error correction decoder circuit coupled to a corresponding one of the at least two equalizers of the equalizer bank and coupled to a corresponding one of the at least two packet decoder circuits.

2. The equalization circuit of claim 1, wherein the second decoder bank includes at least two forward error correction decoder circuits.

3. The equalization circuit of claim 1, wherein each of the at least two equalizers comprises one of a fixed equalizer and an adaptive equalizer.

4. The equalization circuit of claim 3, wherein each of the adaptive equalizers comprises one of a linear equalizer and a nonlinear equalizer.

5. The equalization circuit of claim 3, wherein each of the adaptive equalizers comprises one of a traversal structure and a lattice structure.

6. The equalization circuit of claim 1, wherein the first decoder bank provides a feedback signal to the at least two equalizers of the equalizer bank.

7. The equalization circuit of claim 6, wherein the feedback signal is also provided to the selector circuit to be used in selecting the output of one of the at least two equalizer circuits.

8. An equalization circuit, comprising:

an input adapted to receive signals from a communications channel;

a plurality of equalizer circuits coupled to the input and operable to generate a plurality of intermediate signals;

a selector circuit, responsive to the plurality of equalizer circuits, that selects one of the intermediate signals;

an output coupled to the selector circuit that receives the selected intermediate signal;

a plurality of buffer circuits, each buffer circuit coupled between one of the plurality of equalizer circuits and the selector circuit to buffer the intermediate signals for approximately the duration of a time slot of the communication channel; and

a plurality of error correction decoder circuits coupled in parallel, each decoder circuit coupled to a corresponding one of the plurality of equalizer circuits, wherein each of the plurality of buffer circuits is included in a corresponding one of the plurality of decoders.

9. The equalization circuit of claim 8, wherein each of the plurality of error correction decoder circuits is a forward error correction decoder circuit.

10. The equalization circuit of claim 8, wherein at least one of the plurality of error correction decoder circuits provides a feedback signal to at least one of the plurality of equalizer circuits.