Split computer architecture to separate user and processor while retaining original user interface

• US 7,320,043 B2
• Filed: 09/10/2004
• Issued: 01/15/2008
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Vertiv IT Systems, Inc. (Vertiv Holdings Co.)
• Original Assignee: Avocent Huntsville Corporation (Vertiv Holdings Co.)
• Inventors: Choun, Jeffrey E., Shatas, Remigius G., Thomas, Christopher L., O'Bryant, Greg, Luterman, Greg, Asprey, Robert R.
• Primary Examiner(s): Park; Ilwoo
• Application Number:
  US10/937,511
• Publication Number:
  US 20050044439A1
• Time in Patent Office: 1,222 Days
• Field of Search: 710 62- 64, 710/105, 710/106, 710/300, 710/301, 710/305, 710/306, 710313-315
• US Class Current: 710/105
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: H04L 67/01 Protocols
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.

Claims

1. A system for communicating digital computer data over extended distances comprising:

a processor coupled to a first communication link and generating digital data for communication on the first communication link, wherein the data are communicated according to a standard digital communication format, and wherein the data generated by the processor include information providing video data for use by a video monitor;

a first logic device receiving the digital data generated by the processor and communicated on the first link, the first logic device converting the received digital data into a second digital communication format different from the standard digital communication format, and coupling the converted data to a second communication link different from the first communication link;

a second logic device coupled to the second communication link and receiving the converted data from the first logic device, the second logic device converting the data from the second link into a third digital communication format and coupling the data in the third digital communication format to a third communication link different from the first and second communication links, wherein at least one component of the first logic device is separated from at least one component of the second logic device by at least one clock domain barrier;

a video processing circuit coupled to the third communication link and receiving therefrom at least the information providing video data generated by the processor, the video processing circuit providing the video data in a format suitable for use by the video monitor and transmitting the video data to the video monitor, wherein

said second logic device is constructed and adapted to deliver sideband signals to said first logic device, said sideband signals including (i) an acknowledgement (ACK) signal indicative of successful buffering by said second logic device of data received from said first logic device, and (ii) a negative acknowledgement (NACK) signal indicative of unsuccessful buffering by said second logic device of uncorrupted data received from said first logic device, said unsuccessful buffering being caused by a full buffer at said second logic device,

wherein said second logic device is further constructed and adapted to not send two successive NACK signals without at least one intervening ACK signal indicative of successful buffering of valid data at said second logic device.

2. A system for communicating digital computer data over extended distances according to claim 1, wherein the processor is a microprocessor.

3. A system for communicating digital computer data over extended distances according to claim 1, wherein the standard digital communication format is a PCI data format.

4. A system for communicating digital computer data over extended distances according to claim 1, wherein the first communication link is a PCI bus.

5. A system for communicating digital computer data over extended distances according to claim 1, wherein the second digital communication format is a proprietary, non-standard digital format.

6. A system for communicating digital computer data over extended distances according to claim 1, wherein the second digital communication format is a serial data format.

7. A system for communicating digital computer data over extended distances according to claim 1, wherein the second digital communication format is a packet-based communication format.

8. A system for communicating digital computer data over extended distances according to claim 1, wherein the third digital communication format is the same as the standard digital communication format.

9. A system for communicating digital computer data over extended distances according to claim 1, wherein the data generated by the processor includes video data for use by a video monitor.

10. A system for communicating digital computer data over extended distances according to claim 1, wherein the third digital communication format is a PCI data format.

11. A system for communicating digital computer data over extended distances according to claim 1, wherein the first and third communication links comprise first and second digital communication buses.

12. A system for communicating digital computer data over extended distances according to claim 1, wherein the second logic device receives digital data from a keyboard and a mouse, the second logic device converting the keyboard and mouse data into a format suitable for transmission on the second communication link, and coupling the reformatted keyboard and mouse data onto the second communication link.

13. A system for communicating digital computer data over extended distances according to claim 1, wherein the second communication link comprises a twisted pair medium.

14. A system as in claim 1 wherein said second logic device includes an input FIFO buffer, and wherein said acknowledgement signal is indicative of successful buffering in said input FIFO buffer of data received from said first logic device.

15. A system as in claim 14 wherein said first logic device is constructed and adapted to maintain a saved copy data sent to the second logic device, and wherein said first logic device is further constructed and adapted to delete said saved copy upon receipt of a corresponding acknowledgement signal from said second logic device.

16. A system as in claim 1 wherein said second logic device includes an input FIFO buffer, and wherein said NACK signal is indicative of unsuccessful buffering in said input FIFO buffer of valid data received from said first logic device, said unsuccessful buffering being caused by said input FIFO buffer being full.

17. A system as in claim 16 wherein said first logic device is constructed and adapted to maintain a saved copy of data sent to the second logic device, and wherein said first logic device is further constructed and adapted to retransmit said saved copy upon receipt of a corresponding NACK signal from said second logic device indicative of unsuccessful buffering of said data in said input FIFO buffer of said second logic device.

18. A system as in claim 1

wherein said first logic device is constructed and adapted to maintain a saved copy of data sent to the second logic device, and

wherein said first logic device is further constructed and adapted to delete said saved copy upon receipt of a corresponding acknowledgement signal from said second logic device indicative of successful buffering of said data in said second logic device, and to retransmit said saved copy upon receipt of a corresponding NACK signal from said second logic device indicative of unsuccessful buffering of said data in said second logic device.

19. A system as in claim 1 wherein

said first logic device is further constructed and adapted to deliver sideband signals to said second logic device, said sideband signals including an acknowledgement signal indicative of successful buffering by said first logic device of data received from said second logic device.

20. A system as in claim 1 wherein said second logic device comprises NACK circuitry constructed and adapted to transmit NACK signals, and wherein said second logic device is constructed and adapted to disable said NACK circuitry when a NACK signal is sent and to re-enable said NACK circuitry when valid data are received and successfully buffered and a corresponding ACK signal is sent.

21. A system as in claim 1 wherein said NACK signal is indicative of unsuccessful buffering by said second logic device of valid data received from said first logic device or of uncorrupted data received from said first logic device ahead of an expected sequence.

22. A system for communicating digital computer data over extended distances comprising:

a processor coupled to a first PCI bus and generating digital data for communication on the first PCI bus, wherein the data are communicated according to a PCI communication format;

a first logic device receiving the digital data generated by the processor and communicated on the first PCI bus, the first logic device converting the received digital data into a second digital communication format different from the PCI communication format, and coupling the converted data to a second communication link different from the first communication link;

a second logic device coupled to the second communication link and receiving the converted data from the first logic device, the second logic device converting the data from the second link into the PCI communication format and coupling the data in the PCI communication format to a second PCI bus distinct from the first PCI bus and the second communication link, wherein the at least one component of the first logic device is separated from at least one component of the second logic device by at least one clock domain barrier, wherein

said second logic device is constructed and adapted to deliver sideband signals to said first logic device, said sideband signals including (i) an acknowledgement (ACK) signal indicative of successful buffering by said second logic device of data received from said first logic device, and (ii) a negative acknowledgement (NACK) signal indicative of unsuccessful buffering by said second logic device of uncorrupted data received from said first logic device, said unsuccessful buffering being caused by a full buffer at said second logic device,

wherein said second logic device is further constructed and adapted not to send two successive NACK signals without at least some valid data being successfully buffered by said second logic device between said successive NACK signals.

23. A system for communicating digital computer data over extended distances according to claim 22, wherein the second digital communication format is a proprietary, non-standard digital format.

24. A system for communicating digital computer data over extended distances according to claim 22, wherein the second communication link is an unshielded twisted pair medium between 50 and 100 meters long.

25. A system as in claim 22, wherein the second communication link is between 100 meters and two kilometers long.

26. A system as in claim 25 wherein the second communication link comprises an unshielded twisted pair medium.

27. A system for communicating digital computer data over extended distances according to claim 22, wherein the second logic device receives digital data from a keyboard and a mouse, the second logic device converting the keyboard and mouse data into a format suitable for transmission on the second communication link, and coupling the reformatted keyboard and mouse data onto the second communication link.

28. A system as in claim 22 wherein said second logic device comprises NACK circuitry constructed and adapted to transmit NACK signals, and wherein said second logic device is constructed and adapted to disable said NACK circuitry when a NACK signal is sent and to re-enable said NACK circuitry when valid data are received and successfully buffered and a corresponding ACK signal is sent.

29. A system as in claim 22 wherein said NACK signal is indicative of unsuccessful buffering by said second logic device of valid data received from said first logic device or of uncorrupted data received from said first logic device ahead of an expected sequence.

30. A method for communicating digital computer data over extended distances comprising:

(A) providing a processor coupled to a first PCI bus and generating digital data for communication on the first PCI bus, wherein the data are communicated according to a PCI communication format;

(B) at a first logic device;

(b1) receiving the digital data generated by the processor and communicated in the first PCI bus,

(b2) converting the received digital data into a second digital communication format, the second digital communication format being a proprietary, non-standard digital format different from the PCI communication format, and

(b3) coupling the converted data to a second communication link different from the first PCI bus, said second communication link comprising a medium between 50 meters and two kilometers long; and

(C) at a second logic device coupled to the second communication link;

(c1) receiving the converted data from the first logical device,

(c2) converting the data from the second link into the PCI communication format,

(c3) attempting to buffer said data in the PCI communication format in a buffer of said second logical device;

(c4) upon failure to buffer said data in said FIFO buffer, said failure being caused by said FIFO buffer being full or by said data being ahead of an expected sequence, then, only if the immediately preceding acknowledgement signal was not a NACK signal, sending a sideband NACK signal to said first logic device, said NACK signal being indicative of unsuccessful buffering by said second logic device of uncorrupted data received from said first logic device; and

otherwise

(c5) coupling the data in the PCI communication format to a second PCI bus distinct from the first PCI bus and the second communication link,

wherein at least one component of the first logic device is separated from at least one component of the second logic device by at least one clock domain barrier, and

wherein the second logic device receives digital data from a keyboard and a mouse, the second logic device converting the keyboard and mouse data into a format suitable for transmission on the second communication link, and coupling the reformatted keyboard and mouse data onto the second communication link.