Apparatus and method for memory with bit swapping on the fly and testing
First Claim
1. An information-processing apparatus comprising:
- a first memory having a plurality of addressed locations, each location holding a plurality of bits; and
a first control circuit, the first control circuit including;
a first memory controller, the first memory controller including;
an address-range detector that specifies a range spanning an incrementally variable-length subset of the plurality of addressed locations, wherein the detector allows a plurality of non-power-of-two subset sizes for the range, and that, for each memory request, determines whether an address of the memory request is within the specified range; and
a read-data bit-swap circuit coupled to receive fetched data including a plurality of data bits and one or more spare bits from the first memory and operatively coupled to the address-range detector, and based on an indication from the address-range detector as to whether a memory request address is within the range, to swap one or more, but fewer than all, of the bits of the data, such that one or more spare bits are used for data bits in the read data, and a corresponding number of data bits are not used in the read data.
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Accused Products
Abstract
A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
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Citations
45 Claims
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1. An information-processing apparatus comprising:
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a first memory having a plurality of addressed locations, each location holding a plurality of bits; and a first control circuit, the first control circuit including; a first memory controller, the first memory controller including; an address-range detector that specifies a range spanning an incrementally variable-length subset of the plurality of addressed locations, wherein the detector allows a plurality of non-power-of-two subset sizes for the range, and that, for each memory request, determines whether an address of the memory request is within the specified range; and a read-data bit-swap circuit coupled to receive fetched data including a plurality of data bits and one or more spare bits from the first memory and operatively coupled to the address-range detector, and based on an indication from the address-range detector as to whether a memory request address is within the range, to swap one or more, but fewer than all, of the bits of the data, such that one or more spare bits are used for data bits in the read data, and a corresponding number of data bits are not used in the read data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An information-processing method comprising:
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receiving a first memory request to write data to a memory; detecting whether an address of the first memory request is within a specified range of addresses, wherein the detecting allows an incrementally variable plurality of non-power-of-two sizes for the specified range; remapping a subset of bit positions of a first set of data to form bit-remapped first data based on the address of the first memory request being detected as within the specified range, wherein the remapping means that one or more bits of the first set of data are directed to spare bit positions of the bit-remapped first set of data; and writing the bit-swapped first data to the memory. - View Dependent Claims (24, 25)
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26. An information-processing method comprising:
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receiving a first memory request to write data to a memory; detecting whether an address of the first memory request is within a specified range of addresses; swapping a subset of bit positions of a first data to form bit-swapped first data based on the address of the first memory request being detected as within the specified range; writing the bit-swapped first data to the memory; receiving a second memory request; detecting whether an address of the second memory request is within a specified set of addresses; fetching second data based on a second memory-request address; not swapping bits of the second data based on the second memory-request address being detected as not within the specified set; and changing an end address of the specified set between the second and first memory requests, wherein the second address equals the first address such that data based on the read second data is bit-swapped to produce the first data and written to its same address. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34)
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35. An information-processing system comprising:
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a memory; address checking means for checking the address of each one of a plurality of memory requests from a processor that are transmitted to the memory, wherein the checking allows an incrementally variable plurality of non-power-of-two sizes for a specified range; and means for changing a mapping of bits that are read from and written to the memory, wherein the changed mapping directs one or more bits of a first set of data to spare bit positions of bit-remapped first set of data. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43)
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44. A computer-readable storage medium storing control data thereon for causing a suitably programmed information-processing system to execute a method comprising:
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receiving a first memory request to write data to a memory, detecting whether an address of the first memory request is within a specified range of addresses, wherein the detecting allows an incrementally variable plurality of non-power-of-two sizes for the specified range; remapping a subset of bit positions of a first set of data to form bit-remapped first data based on the address of the first memory request being detected as within the specified range, wherein the remapping means that one or more bits of the first set of data are directed to spare bit positions of the bit-remapped first set of data; and writing the bit-swapped first data to the memory. - View Dependent Claims (45)
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Specification