Thyristor-based device having dual control ports

• US 7,320,895 B1
• Filed: 03/22/2005
• Issued: 01/22/2008
• Est. Priority Date: 11/06/2002
• Status: Expired due to Fees

• Current Assignee: T-Ram, LLC
• Original Assignee: T-RAM Semiconductor, Inc. (Tokai RIKA Company Limited)
• Inventors: Horch, Andrew, Robins, Scott, Nemati, Farid
• Primary Examiner(s): MALSAWMA, LARINFAMKIMA HMAR
• Application Number:
  US11/086,113
• Time in Patent Office: 1,036 Days
• Field of Search: 438/138, 257/E21.529, 257/E21.531
• US Class Current: 438/5
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: H01L 29/7436 Lateral thyristors
• CPC Class Codes: H10B 10/10 SRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components

Abstract

Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port. In this manner, power consumption for a switching operation can be reduced, which is useful, for example, to correspond with reduced power supplied to other devices in a semiconductor device employing the thyristor.

Claims

1. A method for manufacturing a semiconductor device having adjacent thyristor body regions in a substrate, the thyristor body regions being oppositely doped and having a junction therebetween, the method comprising:

etching a trench in a substrate;

lining the trench with an insulative material;

forming conductive material in the trench, separated from a first one of the thyristor body regions by the insulative material and extending above the junction;

etching a portion of the semiconductor device including the conductive material in the trench; and

detecting a characteristic of the material being etched and controlling the etching as a function of the detected characteristic;

wherein detecting a characteristic of the material being etched includes detecting that the conductive material has been etched to a depth that is aligned with the junction.

2. The method of claim 1, wherein detecting a characteristic of the material being etched includes detecting the composition of material being sputtered from the semiconductor device.

3. The method of claim 2, wherein etching a portion of the semiconductor device includes etching a portion of the junction, wherein detecting a characteristic of the material being etched includes detecting that the junction is being etched and wherein controlling the etching as a function of the detected characteristic includes stopping the etching in response to detecting that the junction is being etched.

4. The method of claim 3, further comprising:

forming an insulative material over the etched conductive material in the trench; and

forming a additional conductive material in the trench, said conductive material and additional conductive material forming first and second control ports each adapted for capacitively coupling to the first and second body regions, respectively.

5. The method of claim 2, further comprising implanting the adjacent thyristor body regions while concurrently implanting a dummy portion of the semiconductor device having the junction at the same depth as the junction between the thyristor body regions, wherein etching a portion of the semiconductor device includes etching the dummy portion of the device and wherein detecting a characteristic of the material being etched and controlling the etching includes detecting that the junction in the dummy region has been etched and stopping the etching in response to detecting that the junction in the dummy portion has been reached.

6. A method for manufacturing a semiconductor device having a substrate and a thyristor, the method comprising:

implanting a first region of the substrate;

forming a first control port over the first region and configured and arranged to capacitively couple a first signal to at least the first region;

masking a portion of the substrate at least under the first control port and implanting a second region of the substrate laterally adjacent to the first region;

forming a second control port over the substrate including the second region, the second control port being configured and arranged to capacitively couple a second signal to at least the second region of the substrate, wherein the thyristor is adapted to switch between a blocking state and a conducting state in response to the first and second signals; and

masking a portion of the substrate at least including a portion of the first and second regions and implanting a third region of the substrate laterally adjacent to the second region and separated from the first region by the second region.

7. The method of claim 6, wherein masking a portion of the substrate at least under the first control port and implanting a second region of the substrate includes using the first control port as a mask and aligning a junction between the first and second regions to the mask.

8. The method of claim 6, wherein masking a portion of the substrate at least under the first control port and implanting a second region of the substrate includes using the first and second control ports as a mask and using an angled implant to implant the second region under the second control port.

9. The method of claim 6, wherein implanting a third region of the substrate laterally adjacent to the second region includes using the second control port as a mask and aligning a junction between the second and third regions to the mask.