Offset spacer formation for strained channel CMOS transistor

• US 7,321,155 B2
• Filed: 05/06/2004
• Issued: 01/22/2008
• Est. Priority Date: 05/06/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Wen-Chin, Ko, Chih-Hsin, Ge, Chung-Hu
• Primary Examiner(s): Landau; Matthew C.
• Application Number:
  US10/840,911
• Publication Number:
  US 20050247986A1
• Time in Patent Office: 1,356 Days
• Field of Search: 257/E29.193, 257/391, 257/392, 257/344, 257/409, 257/900, 257/336, 257/408, 257/E29.266
• US Class Current: 257/408
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and source and drain (S/D) regions; wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on a channel region.

Claims

1. A strained channel transistor comprising:

a semiconductor substrate;

a gate dielectric overlying a channel region;

a gate electrode overlying the gate dielectric;

source/drain extension (SDE) regions and source and drain (S/D) regions;

an internally stressed pair of offset spacers disposed adjacent the sides of the gate electrode, said internal stress originating from within said offset spacers, wherein only a portion of a bottom surface portion of each of the pair of stressed offset spacers contacts the semiconductor substrate, said internal stress being compressive for a P charge mobility transistor or tensile for a N charge mobility transistor; and

,

an internally stressed dielectric layer disposed over the gate electrode, the internally stressed offset spacers, and the S/D regions, said internal stress originating from within said dielectric layer;

wherein said stressed offset spacers and stressed dielectric layer are formed with a respective desired level of stress to cooperatively exert a desired strain on the channel region to improve said P or N charge mobility.

2. The strained channel transistor of claim 1, further comprising a pair of L-shaped offset liners disposed along the sides of the gate electrode.

3. The strained channel transistor of claim 1, further comprising respective recessed S/D regions underlying the stressed dielectric layer.

4. The strained channel transistor of claim 1, further comprising conductive regions disposed over the S/D regions.

5. The strained channel transistor of claim 1, wherein the stressed dielectric layer comprises a contact etching stop layer.

6. The strained channel transistor of claim 1, wherein the pair of stressed offset spacers and the stressed dielectric layer are formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.

7. The strained channel transistor of claim 1, wherein the desired stress level is up to about 2 GPa.

8. The strained channel transistor of claim 1, wherein the stressed dielectric layer is formed of a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.

9. The strained channel transistor of claim 8, wherein the desired stress level is up to about 2 GPa.

10. The strained channel transistor of claim 1, wherein the gate dielectric is selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, a high permittivity dielectric, and combinations thereof.

11. The strained channel transistor of claim 10, wherein the high permittivity dielectric is selected from the group consisting of transition metal oxides, rare earth metal oxides, and combinations thereof.

12. The strained channel transistor of claim 1, wherein the gate electrode comprises a material selected from the group consisting of metals, metal suicides, metal nitrides, doped polysilicon, and combinations thereof.

13. The strained channel transistor of claim 1, wherein the semiconductor substrate is selected from the group consisting of silicon, silicon on insulator (SOI), strained silicon, and silicon-germanium.

14. The strained channel transistor of claim 1, wherein the offset spacers have a positive radius of curvature at an outer portion.

15. A strained channel transistor comprising;

an semiconductor substrate;

a gate dielectric overlying a channel region;

a gate electrode overlying the gate dielectric;

recessed source and drain (S/D) regions disposed adjacent opposing sides of the channel region, said recessed (S/D) regions having an upper semiconductor substrate surface level below said gate dielectric level;

a pair of internally stressed offset spacers each having a positive radius of curvature at an outer portion and is formed with said internal stress originating from within said offset spacers at a desired stress level, said offset spacers disposed adjacent the sides of the gate electrode, said internal stress being compressive for a P charge mobility transistor or tensile for a N charge mobility transistor; and

,

an internally stressed dielectric layer, said internal stress originating from within said dielectric layer, said dielectric layer disposed over the gate electrode, the stressed offset spacers, and the recessed S/D regions;

wherein said stressed dielectric layer and said stressed offset spacers to cooperatively exert a strain on the channel region to improve said P or N charge mobility.

16. The strained channel transistor of claim 15, further comprising conductive regions disposed over the S/D regions and underlying the stressed dielectric layer.

17. The strained channel transistor of claim 15, further comprising a pair of L-shaped offset liners disposed along the sides of the gate electrode.

18. A strained channel transistor comprising:

a semiconductor substrate;

a gate dielectric overlying a channel region;

a gate electrode overlying the gate dielectric;

source and drain (3/0) regions disposed on opposing sides of the channel region;

a pair of internally stressed offset spacers formed with said internal stress originating from within said offset spacers at a desired stress level, said offset spacers disposed adjacent the sides of the gate electrode such that only a portion of a bottom surface portion of said offset spacers contacts the semiconductor substrate, said internal stress being compressive for a P charge mobility transistor or tensile for a N charge mobility transistor; and

,

an internally stressed dielectric layer formed with said internal stress originating from within said dielectric layer at a desired stress level, said dielectric layer disposed over the gate electrode including the pair of internally stressed offset spacers and the S/D regions;

wherein said stressed dielectric layer and said stressed offset spacers cooperatively exert a strain on the channel region to improve said P or N charge mobility.

19. The strained channel transistor of claim 18, further comprising conductive regions disposed over the S/D regions and underlying the stressed dielectric layer.

20. The strained channel transistor of claim 18, wherein the offset spacers have a positive radius of curvature at an outer portion.

21. The strained channel transistor of claim 18, further comprising a pair of L-shaped offset liners disposed along the sides of the gate electrode.

22. A strained channel transistor comprising:

a semiconductor substrate;

a gate dielectric overlying a channel region;

a gate electrode overlying the gate dielectric;

a pair of internally stressed offset spacers formed with said internal stress originating from within said offset spacers at a desired stress level, said stressed offset spacers disposed adjacent the sides of the gate electrode such that only a portion of a bottom surface portion of said offset spacers contacts the semiconductor substrate, said internal stress being compressive for a P charge mobility transistor or tensile for a N charge mobility, transistor;

source and drain (S/D) regions disposed on opposing sides of the channel region, said (S/D regions) recessed to have an upper semiconductor substrate surface level below the gate dielectric level; and

,

an internally stressed dielectric layer formed with said internal stress originating from within said dielectric layer at a desired stress level, said dielectric layer disposed over the gate electrode, the stressed offset spacers, and the S/D regions;

wherein said stressed dielectric layer and said stressed offset spacers cooperatively exert a strain on the channel region to improve said P or N charge mobility.

23. The strained channel transistor of claim 22, further comprising conductive regions disposed over the S/D regions and underlying the stressed dielectric layer.

24. The strained channel transistor of claim 22, further comprising an L-shaped offset liner disposed on the sides of the gate electrode.

25. The strained channel transistor of claim 22, wherein the offset spacers have a positive radius of curvature at an outer portion.