Pipelined AD converter capable of switching current driving capabilities

• US 7,321,245 B2
• Filed: 03/25/2004
• Issued: 01/22/2008
• Est. Priority Date: 03/26/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Tani, Kuniyuki, Wada, Atsushi
• Primary Examiner(s): Lam; Tuan T.
• Assistant Examiner(s): Hernandez; William
• Application Number:
  US10/808,575
• Publication Number:
  US 20040189374A1
• Time in Patent Office: 1,398 Days
• Field of Search: 327/538, 327540-543, 327/561, 327108-112, 327/276, 327/277, 327/280, 327/281, 327/287, 327/288, 327/530, 341/161, 341/162, 323/313, 323/316, 323/315
• US Class Current: 327/109
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

A first bias voltage generating circuit which applies a bias voltage to an amplifier circuit of an AD converter has a driving unit and a control unit. The driving unit includes a first bias circuit and a second bias circuit as a plurality of bias circuits which are connected in parallel and have different current driving capabilities. The first bias circuit and the second bias circuit each include a CMOS transistor which is connected directly between a power supply potential and a ground potential, and a switching element which interrupts a feedthrough current. The drains of the CMOS transistors output the bias voltage. The control unit turns on both or either one of the first bias circuit and the second bias circuit, thereby controlling the current driving capability of the entire driving unit.

Claims

1. A bias voltage generating circuit comprising:

a driving unit which generates a bias voltage to be applied to a predetermined load, and

a control unit which switches a current driving capability of the driving unit according to a variation in an amount of current required for the load in a period for applying the bias voltage to the load, wherein

the driving unit includes a plurality of bias circuits which are connected in parallel and have different current driving capabilities,

the control unit switches the current driving capability by controlling the number of circuits to operate out of the plurality of bias circuits,

the plurality of bias circuits output the same bias voltage, and

each of the plurality of bias circuits includes;

a CMOS transistor pair composed of a PMOS transistor and an NMOS transistor which are connected in series between a power supply potential and a ground potential and have a common drain connected to their respective gates, the drain outputting the bias voltage;

a first switching element which interrupts a feedthrough current occurring from the CMOS transistor pair; and

a second switching element which controls output of the bias voltage from the CMOS transistor pair.

2. The bias voltage generating circuit according to claim 1, wherein

the predetermined load is an amplifier which is included in an AD converter.

3. The bias voltage generating circuit according to claim 1, wherein

the control unit controls the number of circuits to operate by sending control signals to the respective switching elements included in the plurality of bias circuits.

4. A bias voltage generating circuit comprising:

a driving unit which generates a bias voltage to be applied to a predetermined load, and

a control unit which switches a current driving capability of the driving unit according to a variation in an amount of current required for the load in a period for applying the bias voltage to the load, wherein

the driving unit includes a plurality of bias circuits which are connected in parallel and have the same current driving capability,

the control unit switches the current driving capability by controlling the number of circuits to operate out of the plurality of bias circuits, and

each of the plurality of bias circuits includes;

a CMOS transistor pair composed of a PMOS transistor and an NMOS transistor which are connected in series between a power supply potential and a ground potential and have a common drain connected to their respective gates, the drain outputting the bias voltage;

a first switching element which interrupts a feedthrough current occurring from the CMOS transistor pair; and

a second switching element which controls output of the bias voltage from the CMOS transistor pair.

5. The bias voltage generating circuit according to claim 4, wherein

the control unit controls the number of circuits to operate by sending control signals to the respective switching elements included in the plurality of bias circuits.

6. A bias voltage generating circuit comprising;

a driving unit which generates a bias voltage to be applied to a predetermined load; and

a control unit which switches a current driving capability of the driving unit according to a variation in an amount of current required for the load in a period for applying the bias voltage to the load,

wherein the driving unit includes a bias circuit configured for outputting a first bias voltage and a second bias voltage which are different from each other, selectively; and

the control unit switches the output of the driving unit between the first bias voltage and the second bias voltage according to a variation in the amount of current necessary for the load,

wherein the bias circuit is a Wilson type current mirror circuit which includes at least a pair of n-channel transistors having different width/length ratios, a pair of p-channel transistors having generally the same width/length ratios, and a switching element which switches the output between the first bias voltage and the second bias voltage.

7. An amplifier circuit comprising:

an amplifier unit which repeats an auto-zero operation and an amplification operation alternately;

a driving unit which supplies the amplifier unit with a bias vo1tage; and

a control unit which switches the current driving capability of the driving unit according to a variation in an amount of current required between the auto-zero operation and the amplification operation of the amplifier unit, wherein

the driving unit includes a plurality of bias circuits which are connected in parallel and have different current driving capabilities,

the control unit switches the current driving capability by controlling the number of circuits to operate out of the plurality of bias circuits, and

each of the plurality of bias circuits includes;

a CMOS transistor pair composed of a PMOS transistor and an NMOS transistor which are connected in series between a power supply potential and a ground potential and have a common drain connected to their respective gates, the drain outputting the bias voltage;

a first switching element which interrupts a feedthrough current occurring from the CMOS transistor pair; and

a second switching element which controls output of the bias voltage from the CMOS transistor pair.

8. The amplifier circuit according to claim 7, wherein

the control unit controls the number of circuits to operate by sending control signals to the respective switching elements included in the plurality of bias circuits.

9. An amplifier circuit comprising:

an amplifier unit which repeats an auto-zero operation and an amplification operation alternately;

a driving unit which supplies the amplifier unit with a bias voltage; and

a control unit which switches the current driving capability of the driving unit according to a variation in an amount of current required between the auto-zero operation and the amplification operation of the amplifier unit, wherein

the driving unit includes a plurality of bias circuits which are connected in parallel and have the same current driving capability,

the control unit switches the current driving capability by controlling the number of circuits to operate out of the plurality of bias circuits, and

each of the plurality of bias circuits includes;

a CMOS transistor pair composed of a PMOS transistor and an NMOS transistor which are connected in series between a power supply potential and a ground potential and have a common drain connected to their respective gates, the drain outputting the bias voltage;

a first switching element which interrupts a feedthrough current occurring from the CMOS transistor pair; and

a second switching element which controls output of the bias voltage from the CMOS transistor pair.

10. The amplifier circuit according to claim 9, wherein

the control unit controls the number of circuits to operate by sending control signals to the respective switching elements included in the plurality of bias circuits.

11. An amplifier circuit comprising:

an amplifier unit which repeats an auto-zero operation and an amplification operation alternately;

a driving unit which supplies the amplifier unit with a bias voltage; and

a control unit which switches the current driving capability of the driving unit according to a variation in an amount of current required between the auto-zero operation and the amplification operation of the amplifier unit,

wherein the driving unit includes a bias circuit configured for outputting a first bias voltage and a second bias voltage which are different from each other, selectively; and

the control unit switches the output of the driving unit between the first bias voltage and the second bias voltage according to a variation in the amount of current necessary for the load,

wherein the bias circuit is a Wilson type current mirror circuit which includes at least a pair of n-channel transistors having different width/length ratios, a pair of p-channel transistors having generally the same width/length ratios, and a switching element which switches the output between the first bias voltage and the second bias voltage.

12. A pipelined AD converter having a plurality of stages of conversion units which generate several bits of digital values of descending order from an input analog voltage, respectively, the AD converter comprising:

an amplifier unit which repeats an auto-zero operation and an amplification operation alternately;

a driving unit which supplies the amplifier unit with a bias voltage; and

a control unit which switches a current driving power of the driving unit according to a variation in the amount of current required between the auto-zero operation and the amplification operation of the amplifier unit,

the control unit controlling the current driving capability so as to drive at least any one of the plurality of stages of conversion units with a relatively high current and drive the other conversion units with a lower current.

13. The pipelined AD converter according to claim 12, wherein the control unit controls the current driving capability so as to drive the first conversion unit at the initial stage with a relatively high current and drive the second and subsequent conversion units with a lower current.