Analog-to-digital converter and semiconductor device

• US 7,321,329 B2
• Filed: 07/06/2006
• Issued: 01/22/2008
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Tooyama, Takayuki, Suzuki, Atsushi, Fukushima, Noriyuki, Nitta, Yoshikazu, Yasui, Yukihiro
• Primary Examiner(s): Barnie; Rexford
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US11/428,970
• Publication Number:
  US 20070008206A1
• Time in Patent Office: 565 Days
• Field of Search: 341/163, 341/126, 341/155, 341/156, 341/159, 341/118, 326/39, 348/245
• US Class Current: 341/163
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

An electronic apparatus includes a CMOS image sensor and a signal processor operable to process an output signal from the CMOS image sensor. The CMOS image sensor includes the following elements: an imaging region; a reference signal generator operable to generate a reference signal; a comparator operable to compare the reference signal generated by the reference signal generator with a signal transmitted from the imaging region; a counter operable to count, in parallel with comparison performed by the comparator, a predetermined count clock and to hold a count value at the time of completion of comparison performed by the comparator; and a reference signal supply interface unit operable to supply the reference signal generated by the reference signal generator to a plurality of comparators via different signal lines, respectively.

Claims

1. An analog-to-digital converter comprising:

a timing controller which generates a clock signal;

a reference signal generator which receives said clock signal and generates a sloped reference signal in synchronization therewith;

a plurality of image elements arrayed in columns and rows, each of which generates an image signal;

a plurality of comparators each of which is arranged to receive as inputs said reference signal, an image signal and said clock signal;

a reference signal interface unit operative to receive said reference signal and to redistribute same to said comparators; and

a plurality of counters, each of which is associated with a respective one of said comparators,

wherein,

each comparator is operative to compare an image signal against said reference signal in synchronization with said clock signal,

the reference signal supply interface unit supplies the reference signal to said comparators via separate signal lines,

the reference signal generator receives control data from said timing controller containing information indicating the slope of the reference signal,

the reference signal generator provides the reference signal with color-dependant variation characteristics and initial values to at least one comparator via the reference signal supply interface unit,

each counter is operable to measure a comparison time of its respective comparator and to hold a count value at the time of completion of comparison performed by the comparator, and

each counter receives at least one data signal from the timing controller indicating up-counting or down-counting.

2. The analog-to-digital converter according to claim 1, wherein the reference signal supply interface unit includes a plurality of buffer amplifiers operable to receive the reference signal generated by the reference signal generator and to supply the reference signal to the comparators via the signal lines.

3. The analog-to-digital converter according to claim 2, wherein the reference signal supply interface unit includes each of the buffer amplifiers associated with a plurality of comparators.

4. The analog-to-digital converter according to claim 2, wherein the reference signal supply interface unit includes the buffer amplifiers each associated with the corresponding comparator.

5. The analog-to-digital converter according to claim 2, wherein the buffer amplifiers have a frequency band equal to or wider than that of the comparators.

6. The analog-to-digital converter according to claim 1, wherein switching means for setting the operating point of comparison is provided at each input stage, to which the reference signal is input, of the plurality of comparators.

7. A semiconductor device for sensing a physical quantity distribution comprising:

a timing controller which generates a clock signal;

a reference signal generator which receives said clock signal and generates a sloped reference signal in synchronization therewith;

a plurality of unit elements;

a charge generator operable to generate a charge corresponding to incident electromagnetic waves;

a unit signal generator operable to generate an analog unit signal in accordance with the charge generated by the charge generator;

a plurality of comparators each of which is arranged to receive as inputs said reference signal, an analog unit signal and said clock signal;

a reference signal interface unit operative to receive said reference signal and to redistribute same to said comparators; and

a plurality of counters, each of which is associated with a respective one of said comparators,

wherein,

each comparator is operative to compare an analog unit signal against said reference signal in synchronization with said clock signal,

the reference signal supply interface unit supplies the reference signal to said comparators via separate signal lines,

the reference signal generator receives control data from said timing controller containing information indicating the slope of the reference signal,

the reference signal generator provides the reference signal with color-dependant variation characteristics and initial values to at least one comparator via the reference signal supply interface unit,

each counter is operable to measure a comparison time of its respective comparator and to hold a count value at the time of completion of comparison performed by the comparator, and

each counter receives at least one data signal from the timing controller indicating up-counting or down-counting.

8. The semiconductor device according to claim 7, wherein the reference signal supply interface unit includes a plurality of buffer amplifiers operable to receive the reference signal generated by the reference signal generator and to supply the reference signal to the comparators via the signal lines.

9. The semiconductor device according to claim 8, wherein the buffer amplifiers each have the same circuit configuration as that of an output stage of the unit signal generator.

10. The semiconductor device according to claim 8, wherein the buffer amplifiers each have a source follower circuit including transistors.

11. The semiconductor device according to claim 10, wherein the transistors included in the source follower circuit each have the same characteristics as those of transistors included in a source follower circuit of an output stage of the unit signal generator.

12. The semiconductor device according to claim 10, wherein the transistors included in the source follower circuit each have the same oxide layer thickness and the same threshold voltage as those of transistors included in a source follower circuit of an output stage of the unit signal generator.

13. The semiconductor device according to claim 10, wherein the transistors included in the source follower circuit have the same size ratio as that of transistors included in a source follower circuit of an output stage of the unit signal generator.

14. The semiconductor device according to claim 7, wherein the unit elements are arranged in a matrix to form the effective region, the plurality of comparators are disposed in a column-parallel manner, switching means for setting the operating point of comparison is provided at each input stage, to which the reference signal is input, of the plurality of comparators, and the switching means are controlled by a common control signal.

15. A CMOS image sensor comprising:

a timing controller which generates a clock signal;

a reference signal generator which receives said clock signal and generates a sloped reference signal in synchronization therewith;

an imaging region providing an image signal;

a plurality of comparators each of which is arranged to receive as inputs said reference signal, an image signal and said clock signal;

a reference signal interface unit operative to receive said reference signal and to redistribute same to said comparators; and

a plurality of counters, each of which is associated with a respective one of said comparators,

wherein,

each comparator is operative to compare an image signal against said reference signal in synchronization with said clock signal,

the reference signal supply interface unit supplies the reference signal to said comparators via separate signal lines,

the reference signal generator receives control data from said timing controller containing information indicating the slope of the reference signal,

the reference signal generator provides the reference signal with color-dependant variation characteristics and initial values to at least one comparator via the reference signal supply interface unit,

each counter is operable to measure a comparison time of its respective comparator and to hold a count value at the time of completion of comparison performed by the comparator, and

each counter receives at least one data signal from the timing controller indicating up-counting or down-counting.

16. An electronic apparatus comprising:

a CMOS image sensor including a imaging region;

a timing controller which generates a clock signal;

a reference signal generator which receives said clock signal and generates a sloped reference signal in synchronization therewith;

a signal processor operable to process an image signal from the CMOS image sensor;

a plurality of comparators arranged to receive as inputs said reference signal, an image signal and said clock signal;

a reference signal interface unit operative to receive said reference signal and to redistribute same to said comparators; and

a plurality of counters, each of which is associated with a respective one of said comparators,

wherein,

each comparator is operative to compare an image signal against said reference signal in synchronization with said clock signal,

the reference signal supply interface unit supplies the reference signal to said comparators via separate signal lines,

the reference signal generator receives control data from said timing controller containing information indicating the slope of the reference signal,

the reference signal generator provides the reference signal with color-dependant variation characteristics and initial values to at least one comparator via the reference signal supply interface unit,

each counter is operable to measure a comparison time of its respective comparator and to hold a count value at the time of completion of comparison performed by the comparator, and

each counter receives at least one data signal from the timing controller indicating up-counting or down-counting.